Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

Help Cyclone V Transciever

Altera_Forum
Honored Contributor II
‎11-22-2014 03:05 PM
1,262 Views

Hello, I am learning the Cyclone V Transceiver PHY IP Core and I have generated a simple project and have one question. I have uploaded my simple project and hope some one can help answer my question. Please see the file Fiber_IO_Block.bdf. On my Transceiver Configuration Controller there is an output port "reconfig_to_xcvr[69..0]". The Altera Transceiver PHY IP Core User Guide says to connect this signal up to the Transceiver PHY port "reconfig_to_xcvr". The "reconfig_to_xcvr" port on the Transceiver is 139 bit wide. So, I'm confused how to connect these two port together if they are not the same bit width. Can some help me? I have zipped up my design.  

 

Thanks, 

joe
Fiber.zip
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎10-14-2017 07:42 PM
531 Views

you need see the number of channels that you setting

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.