Hello, I am learning the Cyclone V Transceiver PHY IP Core and I have generated a simple project and have one question. I have uploaded my simple project and hope some one can help answer my question. Please see the file Fiber_IO_Block.bdf. On my Transceiver Configuration Controller there is an output port "reconfig_to_xcvr[69..0]". The Altera Transceiver PHY IP Core User Guide says to connect this signal up to the Transceiver PHY port "reconfig_to_xcvr". The "reconfig_to_xcvr" port on the Transceiver is 139 bit wide. So, I'm confused how to connect these two port together if they are not the same bit width. Can some help me? I have zipped up my design.
Thanks,
joe
