Help!! Issue with large adder design!!

[Altera_Forum]

Hi, 

 I am trying to build a very large adder, that almost fill all the possible logic elements on the fpga chip, and test it performance. however with the current code, when increase my adder size(currently 8000bits, which is less 2% memory bits, and 2000 logic elements, less than 10% on chip), I got error message: "Error: Selected device has 105 RAM location(s) of type M4K. However, the current design needs more than 105 to successfully fit"  I have searched about this, one suggestion is change the device, but since my aim is full fill the chip, this is not an option.   some people suggest force design use register intead memory blocks, but how can i do that? I am quite new to vhdl & fpga.   I dont know if there is any way I can pass the error, so please help. I have attached my code, FA is a full adder, RCA is a 4 bit adder with 4 FA, CA contain 2000 RCA so should be 8000bit long, ADDER is the shift input from testbench.   Many thanks!!   https://www.alteraforum.com/forum/attachment.php?attachmentid=5967   https://www.alteraforum.com/forum/attachment.php?attachmentid=5968   https://www.alteraforum.com/forum/attachment.php?attachmentid=5969   https://www.alteraforum.com/forum/attachment.php?attachmentid=5970

[Altera_Forum]

my first question - why do you need such a huge adder?

[Altera_Forum]

There are some Quartus II compilation options that doesn't let Quartus optimize your design and transform logic into memory. 

Check the options at assignments->settings

[Altera_Forum]

--- Quote Start ---  There are some Quartus II compilation options that doesn't let Quartus optimize your design and transform logic into memory. Check the options at assignments->settings  --- Quote End ---     yes I can see, but which option is for that? can you tell me more specific?

[Altera_Forum]

assignments->settings-> analysys & synthesis -> more settings 

Select off in the ram/rom replacement/recognizition

[Altera_Forum]

--- Quote Start ---  Hi,   I am trying to build a very large adder, that almost fill all the possible logic elements on the fpga chip, and test it performance. however with the current code, when increase my adder size(currently 8000bits, which is less 2% memory bits, and 2000 logic elements, less than 10% on chip), I got error message: "Error: Selected device has 105 RAM location(s) of type M4K. However, the current design needs more than 105 to successfully fit"   I have searched about this, one suggestion is change the device, but since my aim is full fill the chip, this is not an option.   some people suggest force design use register intead memory blocks, but how can i do that? I am quite new to vhdl & fpga.   I dont know if there is any way I can pass the error, so please help. I have attached my code, FA is a full adder, RCA is a 4 bit adder with 4 FA, CA contain 2000 RCA so should be 8000bit long, ADDER is the shift input from testbench.   Many thanks!!   https://www.alteraforum.com/forum/attachment.php?attachmentid=5967    https://www.alteraforum.com/forum/attachment.php?attachmentid=5968    https://www.alteraforum.com/forum/attachment.php?attachmentid=5969    https://www.alteraforum.com/forum/attachment.php?attachmentid=5970   --- Quote End ---     You don't say what device you targeted but I didn't have any trouble targeting Cyclone IV family. It required 18,000 logic elements, all using logic registers and used 0 embedded memory. QPF and QSF files are attached for you to re-create.   Kevin Jennings

[Altera_Forum]

what should i do? i want to connect a output and a input to a bidr_port.but it always prompt error!!!!!