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Help for Simple Coding of 32Bit Fixed-Point Divider in Verilog

Altera_Forum
Honored Contributor II
‎03-25-2013 10:27 PM
1,572 Views

Sorry if this post might be repeating questions asked in earlier posts (most I checked didn't really help). I am using Verilog to program. 

 

My simple question is as following (it would be nice if the coding is as simple as possible): 

 

given two 32bit fixed-point integers ([31] = signed, [30:10] = integer value, [10:0] = fractional part), divide both inputs (a/b) and return a variable c with the same format. note: i want the divider to be able to output fractional values (i.e. 1 / 4 = .25) 

Thanks!
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Altera_Forum
Honored Contributor II
‎03-26-2013 07:35 AM
717 Views

with fixed point, you treat the inputs simply as integers. You do not need to separate the integer and fractional parts, you just ensure the bits all align properly, and then the results will also be of the same values. note that a 21.11 / 21.11 number will result in a 42.22 result. 

There is a fixed point divider available in the megafunction blocks.
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