Qsys Component Editor for Custom Logic

[Altera_Forum]

Setup: 

Quartus II 12.1 Web Cyclone IV GX transceiver starter board  I'm trying to do something which I thought would be relatively easy, but as been fighting me every step of the way and I would appreciate any and all help. Basically I want to be able to take custom logic in the form of verilog and use it to directly fiddle around in the qsys avalon MM realm. I've attached a project that is incredibly dumbed down (it won't do anything) for clarity but it presents what I'm trying to do if you don't want to read the following explanation.  Lets say I have some RAM in Qsys that I am interested in reading 1 32 bit word from. My previously designed logic is all contained in a top level .bdf so somehow I need to connect blocks and buses to qsys. I figured the best way to approach this is to first use the avalon MM interface spec info and recreate the timing shown there in a verilog file state machine using case statements because its extraordinarily easy to follow. Then using the component editor, load that in, show it the equivalent signal for each of the avalon specific signals, and then connect everything happily in qsys.  Now its not working because it gets hung up waiting for readValidData to be asserted which never happens. This to me means that something isn't getting through. I think the most likely scenario is somehow everything still isn't connected together. I put the verilog file in the synthesis bit, analyzed it, which generated the signals which I then told it were the appropriate avMM signals but it still seems upset (note: it compiles just fine, it just doesn't do anything)  now if anyone knows where in the world I'm going wrong (I am relatively certain I'm following the timing diagram with my state machine, it just doesn't seem to be asking for anything) OR anyone would care to explain to me how my actual project could/can be simulated I would be greatly appreciative. If I am going about this the complete wrong way too, I would be most appreciative but really the goal is just to see if I can communicate over the avalon MM fabric with verilog. RAM is just being used because I figured it was the simplest block to test on.  Many thanks!  sidenote: tried an avalon mm template too with little success and after several hours of battle and a frustrating lack of a timing diagram I gave up on that guy too

[Altera_Forum]

The readdatavalid signal is only used when you are doing pipelined reads, i.e. when the maximumPendingReadTransactions parameter on your avalon MM master interface is not 0. 

When you aren't doing pipelining read, you should use the waitrequest signal instead. When you start reading, put the read signal to 1 and keep it there. Wait for the waitrequest signal to be 0. When it is 0, put the read signal back to 0 and read the data value. Alternatively you can keep your code and set maximumPendingReadTransactions to 1 instead, I think it should work.

[Altera_Forum]

--- Quote Start ---   anyone would care to explain to me how my actual project could/can be simulated I would be greatly appreciative. If I am going about this the complete wrong way too, I would be most appreciative but really the goal is just to see if I can communicate over the avalon MM fabric with verilog. RAM is just being used because I figured it was the simplest block to test on.   --- Quote End ---    You want to look into the Avalon Verification Suite. You basically end up creating a stub Qsys system which exports all of your custom component ports, and then wrapping a testbench around it. You drive the Altera testbench components and it takes care of checking for any protocol violations (like whatever you're looking at right now).  http://www.altera.com/education/training/courses/oavl1100 http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf  Section VII of the PDF has a tutorial.

[Altera_Forum]

This tutorial here: 

 http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  Uses the Verification Suite Avalon-MM BFM for simulation stimulus generation, and the JTAG-to-Avalon-MM bridge in hardware.  You can use that to test your own custom logic in simulation and then hardware (where you can Signaltap II trace your design).  Cheers, Dave

[Altera_Forum]

So thank you all for the notes on simulation. I'll look at that but I would like to explain in very long winded fashion where I'm at on the actual problem: 

 To debug this blasted thing I made 2 attempts at further understanding the problem. First I have a debounced button that goes into qsys via a conduit in my custom component. Within in always at posedge clk begin statement the first line says if the button == 1 (it is active high) then change an output reg to 1 which then goes to an LED (I haven't figured out how to probe stuff directly on a cyc iv gx transceiver starter board yet. After not getting anything from that output ever I decided to take the clock, assign it to an output wire (also a conduit) so I can see what that is doing. It too does nothing (in the zip file the clock isnt set as a differential pair but I've checked the clock and its flipping along just fine).  At this point, I am convinced that there is some kind of disconnect between qsys and everything else in my system. I use a bdf which seems to be the unpopular method of setting up a top level design but thats what I have always done and I think its very easy to see what is going on (and I don't know SV yet). So I have qsys make a block which then gets connected in the top level bdf, so the signals should be getting to qsys. In generating the custom component I only use my logic .v file for synthesis, copy it over for simulation (I'm still not super clear what the difference between those 2 things is) however I noticed examples have a 2nd file which is some kind of interconnecty file so I am starting to wonder if that is somehow what I am missing (I am reffering the 2 files in the box on page 14 of Altera's "Making Qsys Components" pdf). Qsys populates the list of signals when analyzing the .v file, although it sets them all wrong and it needs to be changed. I do NOT have any parameters but I assume those are timing parameters. Lastly all the avalon interrconnect stuff is fine, so I'm really unsure of how I could be losing literally every signal in my design.

[Altera_Forum]

Here, try this example to get you started (its in VHDL, but it should be easy enough for you to understand), and then use the tutorial I linked to above. You can use that to read a PIO (your button) and to write PIOs (LEDs). 

  Cyclone IV GX Starter Kit (C4GXSK) 'basic' design ------------------------------------------------- 3/20/2013 D. W. Hawkins (dwh@ovro.caltech.edu) This top-level basic design can be used as a template for all other C4GXSK designs. 1. Unzip the zip file, eg., into c:/temp/c4gxsk_basic/ 2. Start Quartus II (eg., 12.1sp1) Select the Tcl console (it can be made visible using View->Utility Windows->Tcl Console) Change directory to the zip folder tcl> cd c:/temp/c4gxsk_basic or if you like to copy-and-paste from the Windows Exporer path, you can use paranthesis to 'escape' the windows path format tcl> cd {c:\temp\c4gxsk_basic} 3. Run the synthesis script tcl> source scripts/synth.tcl and you will see the output: Synthesizing the C4GXSK 'basic' design -------------------------------------- - Quartus Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Full Version - Creating the Quartus work directory * C:/temp/c4gxsk_basic/qwork - Creating the design files list * create a new c4gxsk project - Applying constraints - Processing the design - Processing completed The Quartus messages window outputs a few warnings. related to invalid fitter assignments. Those warnings are due to the transceiver channel pin assignments that need to be commented out, since Quartus does not allow you to simply disable (tri-state) those pins (you have to connect them to a transceiver block). 4. Download the design to your board. Per the comments in the top-level file src/c4gxsk.vhd -- This basic design implements the following; -- -- * LED connected to PB -- * LED blinked by a counter clocked by the 50MHz osc -- * LED blinked by a counter clocked by the 125MHz osc -- Enjoy! Cheers, Dave   Cheers, Dave

[Altera_Forum]

So I actually figured out what was wrong... kind of. I didn't realize you needed a top level file to kind of interface between the actual file and qSys. Seems a bit strange since it was able to populate the list of signals but whatever. I now have definitely working conduits, however I guess my avalon MM implementation is off. This is my actual code I've been using to try to figure out what is going wrong. Top level included for completeness' sake. 

 I'm not trying to blow off your simulation comments (again) but this seems to be a protocol implementation? Manythanks  Notes: This is being used to try to talk to RAM initialized with data in it from a .hex Code gets hung up waiting for WaitRequest enable is connected to a debounced PB active high. LEDs are active low  Logic: module ReadRAM(clk,reset,waitR,readData,read,addr,BE,enable,led1,led2,led3); //Avalon Signals input clk,reset,waitR; input readData; output reg read = 0; output reg BE = 'b1111; output reg addr = 'h00000000; //Peripheral Signals input enable output reg led1 = 1; output reg led2 = 1; output reg led3 = 1; integer caseMaster = 0; reg data = 'h00000000; always @(posedge clk) begin case(caseMaster) 0: begin //check enable if(enable==1) begin caseMaster = 1; end end 1: begin //set up registers & go addr = 'h00000000; read = 1; led1 = 0; caseMaster = 2; end 2: begin //wait for RAM to be ready and pull data if (waitR == 0 begin) led2 = 0; data = readData; read = 0; caseMaster = 3; end end 3: begin //if data is good, ping led3. Reset caseMaster if (data != 'h00000000) begin led3 = 0; end if (enable == 0) begin caseMaster = 0; end end endCase end endmodule   What seems to be happening is waitRequest stays high and never comes back down, which means it is never indicating it is ready. This seems to me that it could only be a result that the read request isn't getting there, but I don't understand how that is the case if it is mapped appropriately in the component editor.  Top level connecty file module readRAMInt(clock,reset,waitRequest,readData, read,address,byEn, enable,led1,led2,led3); input clock,reset,waitRequest; input readData; output read; output byEn; output address; input enable; output led1,led2,led3; wire wClock, wReset,wWaitRequest; wire wReadData; wire wRead; wire wAddress; wire wByEn; wire wEnable; wire wLed1,wLed2,wLed3; ReadRAM u1(.clk(wClock),.reset(wReset),.waitR(wWaitRequest), .readData(wReadData),.read(wRead),.addr(wAddress),.BE(wByEn), .enable(wEnable),.led1(wLed1),.led2(wLed2),.led3(wLed3); //Avalon Inputs assign wClock = clock; assign wReset = reset; assign wWaitRequest = waitRequest; assign wReadData = readData; //Avalon Outputs assign read = wRead; assign address = wAddress; assign byEn = wByEn; //User Inputs assign wEnable = enable; //User Outputs assign led1 = wLed1; assign led2 = wLed2; assign led3 = wLed3; endmodule