Assign a part of a register for later use?

[Altera_Forum]

If I have a register like 

signal REG : signed (31 downto 0); and I will use every part of it for other purposes, it'll be a mess if I just take the whole part like  REG (31 downto 24) <= ...  REG (23) <= ...  REG (22) <= ...   Do you know if we can assign it to another description without adding signals? like  Data <= ...  Flag <= ...  ACK <= ... The software will understand Data will be REG (31 downto 24), instead of make another signal and let REG (31 downto 24) <= Data;

[Altera_Forum]

What you want is called an alias, so rather than defining 'signal data : std_logic_vector ...' you would use: 

 alias data is reg(31 downto 24);  Cheers, Dave

[Altera_Forum]

Thank you very much, Dave :)