I'm write code in VHDL to implement a multi-bit generic multiplexer. When I compile it, there was an error that I had no idea how to fix. Can anyone help me? Thank you in advance!
Error message:
Error (10500): VHDL syntax error at GenericMultiplexer.vhd(26) near text ":="; expecting "(", or "'", or "."
line 26 is : temp := temp*2 + sel(i);
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package decoder is
type matrix is array ( natural range <> ) of std_logic_vector ( 7 downto 0 );
end decoder;
library ieee;
use work.decoder.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity GenericMultiplexer is
generic ( n : integer := 8 );
port ( input : in matrix (2**n-1 downto 0);
sel : in bit_vector ( n-1 downto 0 );
output : std_logic_vector ( 7 downto 0 ));
end GenericMultiplexer;
architecture behavior of GenericMultiplexer is
variable temp : integer := 0;
begin
G1: for i in sel'range generate
temp := temp*2 + sel(i);
end generate;
output <= input ( temp );
end behavior;
