Help with Shifting !

Altera_Forum · ‎02-09-2017

Hi everyone,

I am trying to write a vhdl program that takes a input R and a shifted version of it and adds them, then adds the result to a 2nd shifted version of R and then AND's it with a mask. (basically calculating the mod).

Here is the code i have so far but i am not sure how to append Cout to the input of my AND so that i make sure to and S+Cout AND Mask :

PORT

(

R : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

MASK : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

OutRem : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)

 );

END g18_lab2_RNG;

ARCHITECTURE bdf_type OF g18_lab2_RNG IS

COMPONENT g18_lab2

PORT(A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

Cin : IN STD_LOGIC;

S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

Cout : OUT STD_LOGIC

 );

END COMPONENT;

SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC;

SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL RShift1: STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL RShift2: STD_LOGIC_VECTOR(31 DOWNTO 0);

BEGIN

RShift1 <= STD_LOGIC_VECTOR(unsigned(R)sll 1);

RShift2 <= STD_LOGIC_VECTOR(unsigned(R)sll 16);

b2v_inst : g18_lab2

PORT MAP(A => R,

B => RShift1,

Cin => '0',

S => SYNTHESIZED_WIRE_1,

Cout => SYNTHESIZED_WIRE_0);

b2v_inst2 : g18_lab2

PORT MAP(A => RShift2,

B => SYNTHESIZED_WIRE_1,

Cin => SYNTHESIZED_WIRE_0,

S => SYNTHESIZED_WIRE_2,

Cout => ;

OutRem <= SYNTHESIZED_WIRE_2 AND MASK;

END bdf_type;

EDIT: i figured out i can use & to concatenate bits so i changed my Cout to : Cout => SYNTHESIZED_WIRE_3

and then : OutRem <= SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_2 AND MASK;

Altera_Forum · ‎02-10-2017

Are you aware of the 'mod' operator in VHDL?

Have a look at:

http://stackoverflow.com/questions/25848879/difference-between-mod-and-rem-operators-in-vhdl

then have a play with the operator. I think it'll allow you to clean up your code a little... or maybe quite a bit.

Cheers,

Alex