Help with modelling with MODELSIM

[Altera_Forum]

Hello there again, I tried to simulate my first code in MODELSIM. Can someone help me simulate it properly, at the moment I am just a beginner and would like to know if there is any window which can show the errors or why the simulation is not working properly??? 

I just saw few videos on your tube and reached upto here. I have attached a screen shot of my code and simulation window for the experts here. Thanks

[Altera_Forum]

your signal qs needs to be initialised to zeros first at declaration. Quartus wouldn't care about that but modelsim assumes unknown state until you put zero thus the assignment qs(i) <= not qs(i) will always stay U in Modelsim but will toggle in quartus.

[Altera_Forum]

--- Quote Start ---  your signal qs needs to be initialised to zeros first at declaration. Quartus wouldn't care about that but modelsim assumes unknown state until you put zero thus the assignment qs(i) <= not qs(i) will always stay U in Modelsim but will toggle in quartus.  --- Quote End ---    Some progress after your advise, but still a little behind from being ok but lesson 1 learned to always FORCE signal states to 0 to start with. Tried with qs first.

[Altera_Forum]

can you post your latest code (not picture of it) or let me guess: you have set qs to zeros inside process, if so you should not, instead set it to zeros at declaration before begin.

[Altera_Forum]

--- Quote Start ---  can you post your latest code (not picture of it) or let me guess: you have set qs to zeros inside process, if so you should not, instead set it to zeros at declaration before begin.  --- Quote End ---   Here you go Kaz, this code was just thrown at us by our teacher, since I am trying to understand it, watching waveform will surely help. I have attached the downloaded project.

[Altera_Forum]

--- Quote Start ---  Here you go Kaz, this code was just thrown at us by our teacher, since I am trying to understand it, watching waveform will surely help. I have attached the downloaded project.  --- Quote End ---    I changed your signal declaration as follows and it worked, slow clock comes out slow enough to lit the leds. count stays U but it is not doing anything.   signal clks, count : unsigned(ORDER-1 downto 0); signal qs : unsigned(ORDER-1 downto 0) := (others => '0');

[Altera_Forum]

Thanks Kaz, just 1 more question. 

1) What does the following line do? Does it fills the signal with all zeros, regardless of the size?  := (others => '0');  My first simulation works fine now. It is people like you making forums like this useful. Thanks again

[Altera_Forum]

--- Quote Start ---  Thanks Kaz, just 1 more question. 1) What does the following line do? Does it fills the signal with all zeros, regardless of the size?  := (others => '0');   --- Quote End ---    correct and if your vector is two dimensional then you can write := (others => (others => '0'));  I hope now you will lit the leds and impress your teacher soon after holiday.

[Altera_Forum]

--- Quote Start ---  I hope now you will lit the leds and impress your teacher soon after holiday.  --- Quote End ---   Kaz, We have the worst teacher for this subject, everyone relies on you tube and google for learning this.  I wanted to ask few more questions relating to the code if you don't mind: The code is the following: entity ripple_cnt isgeneric (ORDER: natural range 2 to 24:= 19); -- What does this means. Order is of type generic or a keyword of somekind. Can I write Border instead of order? -- Assuming it is not a keyword, the size of ORDER is 22 is that correct? -- The value of order is 19, Correct? Is this value in binary 19? port( fast_clk: in std_logic; slow_clk: out std_logic); end ripple_cnt; architecture structure of ripple_cnt is --internal signals signal clks, count : unsigned(ORDER-1 downto 0); -- I am confused, if I assume size of ORDER is 22, the ORDER-1 to 0 should give me size of 21 down to 0 but in my simulation window the clks and count are of the size 20 downto 0. Why is that? signal qs : unsigned(ORDER-1 downto 0):=(others=>'0'); -- Same question as above for this as well begin slow_clk <= qs(ORDER-1); clks(0) <= fast_clk; -- Cascade the FFs to implement Ripple Counter clks(ORDER-1 downto 1) <= qs(ORDER-2 downto 0); -- Implement Toggle FFs ASYNCH_CNT: for i in 0 to ORDER-1 generate -- What does generate do? I read about loop but don't know what generate means here? T_FF:process(clks) is begin if rising_edge(clks(i)) then qs(i) <= not qs(i); -- Implements a T_ Flip Flop end if; end process T_FF; end generate; end structure;  Thanks a lot.

[Altera_Forum]

--- Quote Start ---   Kaz, We have the worst teacher for this subject, everyone relies on you tube and google for learning this.  I wanted to ask few more questions relating to the code if you don't mind: The code is the following: ..snip..   --- Quote End ---   entity ripple_cnt isgeneric (ORDER: natural range 2 to 24:= 19); -- What does this means. Order is of type generic or a keyword of somekind. Can I write Border instead of order? -- Assuming it is not a keyword, the size of ORDER is 22 is that correct? -- The value of order is 19, Correct? Is this value in binary 19? -- "ORDER" is the identifier name, "natural range 2 to 24" is the type, just "natural" could also be used. You can change "ORDER" to "Border" if you want. -- The range of ORDER is 23 different values. -- ":= 19" defines a default value. When you instantiate the component in other VHDL code, you can change this value, or if you do not specify a value, 19 will be used. port( fast_clk: in std_logic; slow_clk: out std_logic); end ripple_cnt; architecture structure of ripple_cnt is --internal signals signal clks, count : unsigned(ORDER-1 downto 0); -- I am confused, if I assume size of ORDER is 22, the ORDER-1 to 0 should give me size of 21 down to 0 but in my simulation window the clks and count are of the size 20 downto 0. Why is that? -- I believe you need to look at the instantiation of the component in your testbench code. Are you changing the value of ORDER? -- Looking at your last screenshot, the size of "clks" looks normal. ORDER = 19, so "clks" should be an STD_LOGIC_VECTOR(18 DOWNTO 0) signal qs : unsigned(ORDER-1 downto 0):=(others=>'0'); -- Same question as above for this as well begin slow_clk <= qs(ORDER-1); clks(0) <= fast_clk; -- Cascade the FFs to implement Ripple Counter clks(ORDER-1 downto 1) <= qs(ORDER-2 downto 0); -- Implement Toggle FFs ASYNCH_CNT: for i in 0 to ORDER-1 generate -- What does generate do? I read about loop but don't know what generate means here? -- Generate used with a for loop will instantiate one component several times. -- It is useful since you can use the loop variable for clever things, and saves you some typing. -- In this instance, that process statement is being generated ORDER number of times, with "i" changing each time. T_FF:process(clks) is begin if rising_edge(clks(i)) then qs(i) <= not qs(i); -- Implements a T_ Flip Flop end if; end process T_FF; end generate; end structure;  Hope this helps.

[Altera_Forum]

Thanks Zeboul. It makes all the sense in the world now. All going down well upto now. 

I have a question about the simulation again. I have attached the screen shot and would like to know why some waves start from the middle. I would like to see all waveforms from a common starting point. Any pointers?  Thanks

[Altera_Forum]

It is because you have added few nodes first then you started running simulation then stopped it then added more nodes then you continued running simulation.  

All you have to do is add all nodes from start then run your simulation.

[Altera_Forum]

--- Quote Start ---    -- Implement Toggle FFs  ASYNCH_CNT: for i in 0 to ORDER-1 generate -- what does generate do? i read about loop but don't know what generate means here?  T_FF:process(clks) is  begin  if rising_edge(clks(i)) then  qs(i) <= not qs(i); -- Implements a T_ Flip Flop   end if;  end process T_FF;  end generate;   --- Quote End ---    Does it mean that I can write this as the following:   --- Quote Start ---    -- Implement Toggle FFs  --ASYNCH_CNT: for i in 0 to ORDER-1 generate   T_FF1:process(clks) is  begin  if rising_edge(clks(0)) then  qs(0) <= not qs(0); -- Implements a T_ Flip Flop   end if;  end process T_FF1; : : : : :  T_FF20:process(clks) is  begin  if rising_edge(clks(20)) then  qs(20) <= not qs(20); -- Implements a T_ Flip Flop   end if;  end process T_FF20;  --end generate;   --- Quote End ---  

[Altera_Forum]

no because you need to use edge of each clk separately (clks is multiple clocks) 

 edit:  oops sorry.if you want that many processes then you can

[Altera_Forum]

As you have found out yourself the generate is unfolded by compiler into that many processes. 

Normally we can use for loop but because you can't put for loop ahead of process then generate is useful here. The actual purpose of generate is to tell compiler to synthesise or not depending on some condtions but here we borrowed it as loop that always generates