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17268 Discussions

Help with reseting counet

Altera_Forum
Honored Contributor II
1,728 Views

Hey, I've written a simple counter code 

When the cnt = 5 the  

signal std_logic_vector Inc +'1' 

Now I want you end this process when  

It's equal to "1111"; 

 

Everytime I try to end this I see In the waveform simulation the it just beginning from" 0000" again. 

What can I do?
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Altera_Forum
Honored Contributor II
939 Views

Why not post the code and be a more descriptive of the problem.

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Altera_Forum
Honored Contributor II
939 Views

Entity VCO is 

Port(sw:in std_logic; 

Clk:in std_logic; 

Bit_4: out std_logic_vectot(3 downto 0)); 

End entity; 

 

Architecture behave of VCO is 

Signal cnt: integer range 0 to 50000000:=0; 

Signal f_out: std_logic_vector(3 downto 0):=x"0"; 

Begin 

 

Process (clk)  

Begin 

 

If sw = '1' then 

 

If clk 'event and clk=' 1' then 

Cnt<=cnt+1; 

 

If cnt=5 then 

F_Out<=f_out+'1'; 

Cnt<=0; 

Elsif cnt=5 then 

If f_out="1111" then 

F_out<="1111" 

Cnt<=0; 

End if; 

End if; 

End if; 

 

Elsif ='0' then 

Cnt<=0; 

F_out<="ZZZZ"; 

End if; 

End process; 

Bit_4<=f_out; 

End;
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Altera_Forum
Honored Contributor II
939 Views

I want when f_out="1111" 

The counter will stop end remain on "1111"  

Instead of looping end start counting from 0000 again
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Altera_Forum
Honored Contributor II
939 Views

What is F_F_out - it's not declared in your code. 

Assuming this is a typo - then your code will never have f_out locked at "1111" because the only situation where you check for "1111" also resets cnt. 

maybe you need the  

 

if f_out = "1111" then 

 

To have the highest prirotiy. 

 

On a side note - why have you got the sw signal as an asynchronous enable? this is bad practice - it should be a synchronous enable.
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Altera_Forum
Honored Contributor II
939 Views

I've tried this it didn't work..  

It shows me in the simulation the same thing 

 

 

And I don't have sw signal  

It is a toggle sw for on/off use
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Altera_Forum
Honored Contributor II
939 Views

Tried what? I dont see any new code. 

 

Have you tried this: 

Process (clk) Begin If clk 'event and clk=' 1' then Cnt<=cnt+1; if f_out /= "1111" then If cnt=5 then F_Out<=f_out+'1'; Cnt<=0; Elsif cnt=5 then If f_out="1111" then F_F_out<="1111" Cnt<=0; End if; End if; end if; End if; End process;
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Altera_Forum
Honored Contributor II
939 Views

 

--- Quote Start ---  

Tried what? I dont see any new code. 

 

Have you tried this: 

Process (clk) Begin If clk 'event and clk=' 1' then Cnt<=cnt+1; if f_out /= "1111" then If cnt=5 then F_Out<=f_out+'1'; Cnt<=0; Elsif cnt=5 then If f_out="1111" then F_F_out<="1111" Cnt<=0; End if; End if; end if; End if; End process;  

--- Quote End ---  

 

 

Thanks man! It worked 

I don't know how I didn't think about "/=" inequality
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