Hide I/Os in higher Design Levels

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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Hide I/Os in higher Design Levels

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Hey.

I am developing an easy logical system which is controlled by a NIOS Processor. Therefore I have now on the one side the Schematic File with all the I/O ports for the Nios Proce3ssor and the external memory and on the other side the logical system developed with the Megafunctions.

Now I wanted to bring them together in one top level schematic file. The Logic System is reduced a lot by using the "Create Symbol of Current File" Feature but if I do the same for the NIOS system I still have all the I/Os which I need for the external DDR2 RAM. But i would like to reduce so that I have only the I/Os which communicate with the other system.

Is there an way to do it? I tried it with virtual Pins but so far no success.

Thanks.

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