Hierarchical Name Reference in QII

Altera_Forum · ‎12-09-2011

Hi,

I'm trying to get signals out of my modules for debug, and I don't want to route them through 50 levels of hierarchy, I just want to reference them in my top module. BUT, it doesn't work in QII! isn't it a basic Verilog syntax?

here's what I do:

----------------------------

A a_inst(...);

assign debug = a_inst.<some internal signal>;

----------------------------

The error I get is at synthesis time (not fitter):

----------------------------

Error (10207): Verilog HDL error at ...(...): can't resolve reference to object "..."

----------------------------

Any help is appreciated.

Altera_Forum · ‎12-09-2011

this feature is only supported within the same module...which basically means its not supported:

http://quartushelp.altera.com/current/mergedprojects/hdl/vlog/vlog_list_support.htm

maybe try SignalTap? or the Logic Analyzer interface (i've never actually used this feature)

Altera_Forum · ‎12-09-2011

thanks very much, to be honest it's easier/faster to route signals than using signal tap haha! that thing is so messy and buggy and ... I just don't have good experience with signal tap :) I prefer to make my own debug infrastructure.