Fatal Error: Stack Overflow

Altera_Forum · ‎12-08-2011

Hi,

I'm wiring basically long delay lines using a lot of NOT gates.

When I exceed 7600 gates in a row (without any flip flops or clocks), Quartus won't compile my project anymore, but I just get the following error:

*** Fatal Error: Stack Overflow

Module: quartus_map.exe

Lock in use: 9

Stack Trace:

0x4758e: STA_TDC_CLOCK_INTERFACE::has_a_clock + 0x2e8e (TSM_STA)

0x47943: STA_TDC_CLOCK_INTERFACE::has_a_clock + 0x3243 (TSM_STA)

.......(approximately 30 times the same line repeated)

End-trace

Quartus II 64-Bit Version 11.1 Build 173 11/01/2011 SJ Full Version

My Verilog program looks basically like this:

assign delay_wire[1] = ~delay_wire[0];

assign delay_wire[2] = ~delay_wire[1];

....

Please help me with this problem!

Thank you,

David

Altera_Forum · ‎12-08-2011

wow, that is an interesting feat

STA must be static timing analyzer, so you might turn off timing driven synthesis and maybe physical synthesis - anything that has to do with analyzing the timing of your logic

have you tried cascading blocks of say 1000 inverters instead of putting it all in one source file?

unfortunately i don't think this a difficult thing for Altera to support because the delay will not be compensated over PVT, so you may have trouble getting a proper fix. either way you could file an SR at http://mysupport.altera.com

Altera_Forum · ‎12-09-2011

Thank you.

I changed the settings and got rid of everything with clocks. Now I can implement more inverters without errors, but still get the same message when I introduce more than 20000 inverters.

So it has to be some kind of software issue with Quartus, right?

Altera_Forum · ‎12-09-2011

yes, it must be. but like i said its in a bit of a grey area of support

curious, what is your delay goal?