High-impedance state when simulate FIFO IP core using Modelsim altera

Altera_Forum · ‎10-30-2015

I have generated the FIFO IP-core Using Quartus 12.1 ,and simulated it with Modelsim-altera starter edition. The top-test file and the incentives are as follows:

//---------------------top_test---------------------------------------------------------------------

`timescale 1ns/1ns

module top_test(

output [31:0] q ,

output empty,

output full

);

wire [31:0] data;

wire data_val;

reg rd_req;

reg data_val_0,data_val_1;

always@(posedge clk) data_val_0<=data_val;

always@(posedge clk) data_val_1<=data_val_0;

always@(posedge clk) rd_req <= data_val_1;

clk_reset_gen clk_reset_gen(

.clk (clk),

.reset_n (reset_n)

);

data_gen data_gen(

.clk (clk ),

.reset_n (reset_n ),

.data (data ),

.data_val (data_val)

);

fifo_bbbb fifo_bbbb(

.aclr (~reset_n),

.clock (clk),

.data (data),

.rdreq (rd_req),

.wrreq (data_val),

.empty (empty),

.full (full),

.q (q)

);

endmodule

//---------------------clk_reset_gen------------------------------------------------------------------------

`timescale 1ns/1ns

module clk_reset_gen(

output reg clk,

output reg reset_n

);

initial begin

clk =1'b0;

reset_n =1'b0;# 1000 reset_n =1'b0;# 10000 reset_n =1'b1;

end

always# 10 clk = ~clk;

endmodule

//----------------------data_gen-----------------------------------------------------------------------

module data_gen(

input clk,

input reset_n,

output [31:0] data,

output data_val

);

reg [8:0] counter;

always@(posedge clk or negedge reset_n)begin

if(~reset_n) counter<='b0;

else counter<=counter+1'b1;

end

assign data = {counter[7:0],counter[7:0],counter[7:0],counter[7:0]};

assign data_val = counter[8];

endmodule

http://www.alteraforum.com/forum/attachment.php?attachmentid=11341&stc=1

//-----------end----------------------------------------------------------------

I have compiled the files ：test_top.v,clk_reset_gen,data_gen,fifo_bbbb.v,220model，altera_mf into the same library，but all the output signals are high-impedance state.When I starting the modelsim_altera through the Nativelink to simulate ，I got the same result . Please help me ,thank you very much ! !

DNguy4 · ‎12-04-2018

Hi,

Did you find out the cause of this? I see something similar with my design.

Thanks