Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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16023 Discussions

High logic bloat for Platform Designer Interconnect

Honored Contributor II


I'm a little bit confused about the Avalon MM Interconnect generator in the Platform Designer: I have one EMIF (128b, 233.25 MHz) as Avalon Slave and one Avalon Master (DMA, 128b, same clock), and have connected them directly together in the Platform Designer (without any other slaves or masters). Since I'm using bursts, I expect some kind of logic that transforms these bursts into multiple requests (I guess that's the "translator"), but I'm not sure why there is a response FIFO ("agent_rsp_fifo"), and why it takes so much resources (altera_avalon_sc_fifo instance, 65 depth, 225 bit width, MLAB). As far as I understand, masters are required to have the capability of receiving all read responses directly, as no ready signal exists. Any idea? 


Thank, dzo
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Honored Contributor II

The response FIFO stores responses from a slave to send back to a master. It's always included in a master/slave connection, but it might seem larger with EMIF because the EMIF IP can do bursts, as you mention, but also performs address and data reordering to reduce how often rows in the external memory need to be precharged.