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DNguy4
Beginner
692 Views

How Quartus route clock after pll?

Hi,

If i have the same clock going to two registers, Quartus will ensure that the clock arrives at these two registers at the same time for synchronous design.

If I have two clocks with the same frequency from two output pins of a pll going to two registers, will Quartus ensure that these two clock arrive at the same time? or it will treat them as two independent clocks? I think it will treat them as two independent clocks but just want to double check.

Thanks

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3 Replies
JonWay_C_Intel
Employee
30 Views

Hi @DNguy4​ Yes, it will be treated as 2 independent clocks.

DNguy4
Beginner
30 Views

Thank you JwChin. To synch those clocks, the only option is the max/min skew in the constrain, right?

JonWay_C_Intel
Employee
30 Views

Hi @DNguy4​ , if you have 2 independent clock, most probably PLL will route them to 2 different GCLKs. The skew between each GCLK is minimum. If you would like to constrain, you can constrain them to different GCLK and see which GCLK combination has the lowest skew.

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