If i have the same clock going to two registers, Quartus will ensure that the clock arrives at these two registers at the same time for synchronous design.
If I have two clocks with the same frequency from two output pins of a pll going to two registers, will Quartus ensure that these two clock arrive at the same time? or it will treat them as two independent clocks? I think it will treat them as two independent clocks but just want to double check.
Hi @DNguy4 , if you have 2 independent clock, most probably PLL will route them to 2 different GCLKs. The skew between each GCLK is minimum. If you would like to constrain, you can constrain them to different GCLK and see which GCLK combination has the lowest skew.