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How can I use altera_avalon_sc_fifo in a VHDL simulation?

ONors
New Contributor I
1,090 Views

I use altera_avalon_sc_fifo (Avalon_ST Single Clock FIFO) in qsys. When I generate HDL I select VHDL for simulation I get <qsys_name>/altera_avalon_sc_fifo_161/sim/altera_avalon_sc_fifo.v and <qsys_name>/<subsystem_name>/sim/<qsys_name><subsystem_name>_<gibberish>_sc_fifo_<instance_name>.vhd.

 

altera_avalon_sc_fifo.v compiles in Modelsim, but the vhd file does not.

If I comment out these lines it compiles.

for sc_fifo_n0 : altera_avalon_sc_fifo use entity jesd204b_ed_qsys_altera_avalon_sc_fifo_161.altera_avalon_sc_fifo;

Now I can instantiate the fifo in my testbench and compile the testbench. In modelsim I can see the sc_fifo componet under the sim tab as an instance of the design unit altera_avalon_sc_fifo. I can look into the hierarchy of the instance and I see the Verilog parameters as I expect them to be, I see the nets and registers. However the instance does nothing. I see a valid packet coming in but nothing going out, except for valid. The same FIFO works in hardware.altera_avalon_sc_fifo.png

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1 Reply
AnandRaj_S_Intel
Employee
158 Views

Hi,

 

If possible can you share the project ?

Issue may be due to bench.

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

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