How can I verify if a module of a design meets the timing requirements?

[Altera_Forum]

Is there any way to verify whether a custom module(qsys component with a avalon streaming input, output and an avalon master slave) meets the timing requirements without having to compile an entire design using that module?

[Altera_Forum]

There are many factors that can have an impact on a module's timing performance, and this includes what is around that module, how it is connected to the other ones, how many resources in the FPGA are used, routing.... so you need the full design. 

That said, you can create a side project with your module alone in the component, add some constraints for the clocks and the inputs-outputs, and compile it. It can help troubleshoot a few things and if this fails to meet the timing requirements, then there is little hope the full design will. The opposite is unfortunately not true, if the small project meets all timing requirements, there is no guarantee the same component in the bigger project will.