Initialize signal with random number

Altera_Forum · ‎02-12-2013

I'd like to intitialize one of my signals with a random number. The only way I know how to use random numbers in vhdl is with the UNIFORM statement in a testbench loop. Is there a way to assign a random number in an architecture block?

Right now I'm doing it the following way, but getting errors due to the shared variable.


shared variable pncomp_seed : std_logic_vector(width -1 downto 0);
begin
 clk_wire <= clk;
 output<= final_output_wire;
 isvalid <= valid_wire;
 
 -- Calculate seeds 
process
variable internal_seed1,internal_seed2 : positive;
variable rand_num : real;
variable int_rand_num : integer;
begin
 UNIFORM(internal_seed1,internal_seed2,rand_num);
 int_rand_num := INTEGER(TRUNC(rand_num*256.0));
 pncomp_seed := std_logic_vector(to_unsigned(int_rand_num,pncomp_seed'length));
 end process;
 
 seed_wire <= pncomp_seed;

Altera_Forum · ‎02-13-2013

Is this part of a test bench or a synthesizable design? The uniform function is most probably not synthesizable. I think the only way to use it is to put it in a process and initialize your signal from there. The Uniform call modifies the seeds, so it can't just be used as an initialization constant.

What exactly are you trying to achieve? Even in a test bench, if your seed values are initialized with a constant value, the Uniform call will return you the exact same sequence of "random" number at each run.

Altera_Forum · ‎02-13-2013

You Can use the uniform function, but not in a process. It has to be used inside an initialisation function. But the problem is going to be the seeds need to come from somewhere, and Quartus wont let you store the seeds between function calls (theres no problem with this in VHDL per se via shared variables, but quartus doesnt like it). So you end up having to use a generic anyway.

So the answer is No for synthesisable code.