Re: How can i save a constant value on a FPGA for a comparison?

Altera_Forum · ‎03-30-2015

Hello,

i'm searching for a easy way to save a constant value (std_logic_vector) on a FPGA. For example, i need to save something like that: 101000101010010, because i want to compare two bitstrings. At frist i create such a Bitstring on the FPGA with some ring oscillators and then i save it on the FPGA with copy and paste. After this i want to create a new one to compare it with the first one. After this the FPGA shows the difference. The creation (http://www.dict.cc/englisch-deutsch/creation.html) and the comparison is done by a controller.

I tried it like this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity verification_reg is
    
    generic (
      bit_length    : integer := 3160
    );
    
    port (
    -- Output port    
      verification_responses_out                : out std_logic_vector((bit_length - 1) downto 0)
    );
end verification_reg;
architecture arch of verification_reg is
    
   begin
      verification_responses_out <= "00000000000000000000000..........00111111"
end arch;

It works, but i have a Problem. I create and save such a Bitstring, but this saved bitstring confuses the ring oscillators on the FPGA. The difference between the "old" and "new" bitstring is very high. If i don't change the saved bitstring the difference is very small. Is it possible to save a bitstring on the FPGA, without to confuse the FPGA?

Thank you for the help and sorry for my very bad english. :)

Mime

Altera_Forum · ‎03-31-2015

Reemerge that any change to your code will modify the place and route. I assume these ring oscillators are made using logic? So any changes will modify their behaviour.

The only way to force this will be to lock the ring oscillators in place (which will be a get long and tedious task) or pre compile the ring oscillators into a a post p&r netlist.

Why do you hate doing oscillators anyway?

Altera_Forum · ‎03-31-2015

Hi!

Yes, the ROs are made using logic.

I forgot to say, that i tried it with "logic lock regions" without a better result. Still a very high difference. What do you mean with lock the ring oscillators?

And could you explain shortly how i can pre compile the ROs into a post p&r netlist.

I don't understand your last sentence, why should i "hate" this? :D

Sorry my english is very bad :D

Altera_Forum · ‎03-31-2015

Logic lock regions are going to be no good - it will still spread the logic around differently on each compilation. You will need to manually place and route each lut and register yourself to get a consistant result.

I dont know how to make a pre-compiled netlist, I have never done it - Ill let someone else answer,.

But your ring oscillators are going to affected by PVT - process voltage temerature. Their frequency and duty cycle will change according to these uncontrollable factors.

The last sentence is due to auto text from my phone. I meant to say - why do you have ring oscilators? they are far to prone to PVT and P&R changes. Why not just use a PLL?