How declare ALM synchronous signal (enable, sload, sclear) in vhdl

[Altera_Forum]

Hello. 

The basic cell in Intel FPGA have a wonderful architecture, including dedicated synchronous signals as enable, sload and sclear. However, describe the use of this resources is not easy in vhdl for me. I use "process" only for declare hardware associated whit registers. Declare "enable" is easy: if (enable) then --this use enable dedícate port  q <= xxxx; end if; Declare "sclear"... if (sclr) then  --this use in RTL and Chip Planner a mux! i want sclr dedícate port  q <= (others => '0'); end if; Declare "enable" and "sclear" use two mux. Now don't use enable dedícate port.  How can use these precious resourses, synchronous dedícate ports?  Thanks!! [sub][/sub]

[Altera_Forum]

You can access a complete template for all secondary control signals using the Edit menu in the Quartus text editor. But here is a similar complete template. Just remove the signals you don't want to use: 

 ARCHITECTURE behavior OF dff IS BEGIN PROCESS(clk, aclr, apre, aload, adata) BEGIN IF aclr = '1' THEN q <= '0'; ELSIF apre = '1' THEN q <= '1'; ELSIF aload = '1' THEN q <= adata; ELSIF rising_edge(clk) THEN IF ena = '1' THEN IF sclr = '1' THEN q <= '0'; ELSIF sload = '1' THEN q <= sdata; ELSE q <= d; END IF; END IF; END IF; END PROCESS; END ARCHITECTURE behavior;