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Altera_Forum
Honored Contributor I
1,308 Views

Nios II read/write to DDR3 using external DDR3 controller

Hello, 

I have a simple Qsys SoC consisting of Nios II, on-chip memory, 2 Avalon MM masters and 1 AXI slave. I have connected the Nios II to each Avalon MM master (one for read and one for write, would this be correct?), and these 2 Avalon MM masters are in turn connected to the AXI slave. The AXI interface of the AXI slave is exported and is connected to the external DDR3 controller. It is not possible to add the DDR3 controller in Qsys because I am working with a preset framework (I am using a Pico M506 board with a Stratix V FPGA). 

I have two questions: 

1. If I want to Nios II to write data to DDR3, what memory address should I reference? Should it be from the address range of the write Avalon MM master? I have tried this but it seems to not be working. 

2. Am I right to use two Avalon MM masters? I find that the cp port of an Avalon MM master can only be connected to one of either read_cp or write_cp of the AXI slave. 

 

I have attached an image of the Qsys SoC.https://alteraforum.com/forum/attachment.php?attachmentid=14459&stc=1  

 

Thanks.
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5 Replies
Altera_Forum
Honored Contributor I
150 Views

Your picture is way too small. What are the Avalon masters you are referring to? What are the instruction and data masters of the processor connected to?

Altera_Forum
Honored Contributor I
150 Views

Sorry about the image. Hopefully the one I have uploaded now is visible. In the SoC, the Nios II instruction and data master are connected to on-chip RAM, and the data master is also connected to the 2 Avalon MM master agents. The master agents are in turn connected to an AXI slave, the AXI interface of which is exported for connecting to the external DDR3 controller. I have programmed the OCRAM with a .hex file generated in Eclipse. In this program, I'm trying to get the Nios II to write to DDR3. But it doesn't seem to work. https://www.alteraforum.com/forum/attachment.php?attachmentid=14473

Altera_Forum
Honored Contributor I
150 Views

Also, am I right to assume that the address range of the write Avalon MM master agent can be used to get the Nios II to write to DDR3?

Altera_Forum
Honored Contributor I
150 Views

This looks correct and the addressing should be the address you put on the master agents. The address would get passed through to the AXI interface but only the offset. In other words, when you perform a read, you access 0x2xxx_xxxx to access the read master agent, but the address passed to the AXI interface would be the offset. So 0x2000_0000 would do a read at DDR memory address location 0x0000_0000. I don't know if this helps.

Altera_Forum
Honored Contributor I
150 Views

I have tried this, I used the following simple code in Eclipse to get Nios II to write to DDR3 

int *mem = (int *)MERLIN_MASTER_AGENT_1_BASE; 

*mem = 0xdeadbeef 

 

I generated a .hex file and put it on the OCRAM. However, the write to DDR3 doesn't happen. When I read the DDR3 contents in software, the word I programmed Nios II to write is not present.
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