Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How do I determine the cause/source of an Intel FPGA IP Evaluation Mode constraint in a Quartus Prime Standard compilation?

GCord
Beginner
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Quartus Prime Standard is reporting "12188 Intel FPGA IP Evaluation Mode feature is turned on for the following cores", but then does not list anything "following" except to note "265072 Messages from megafunction that supports Intel FPGA IP Evaluation Mode feature", "265069 Megafunction that supports Intel FPGA IP Evaluation Mode feature will stop functioning 1 hour after device is programmed", and "265071 Evaluation period of megafunction that supports Intel FPGA IP Evaluation Mode feature can be extended indefinitely by using tethered operation".

 

I do not know what megafunction is the source of this complaint, nor what must be done to eliminate the constraint.

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sstrell
Honored Contributor III
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What IP are you using in your design?

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