How do we see the internal signal of a design in Quartus II simulator

[Altera_Forum]

Hi,  

 I am not able to see the waveforms corresponding to the internal signals, which are actaully pins of subdesigns in a hierarchical design.   I am able to see only the waveforms corresponding to the pins of top level module. My design is in verilog.   I added the pins of subdesigns using nodefinder in .vwf file but after simulation, the warnings say that  "Warning: Ignored node in vector source file. Can't find corresponding node name "pll:pll_inst1|locked" in design."   Could anyone help me in resolving the problem please?   Thanks, Kapil

[Altera_Forum]

Try to acquire the signal at the actual source, the "xxx:auto_generated" entity.

[Altera_Forum]

Thanks for the reply! 

 I tried selecting the internal node by going to the internal module, but it seems like when the signal actually comes up to the waveform, then the highest module name does'nt show up.   For example, in my case the top level module name is "clk_divider" and it instantiates pll inside it. But when I choose the pins on pll instance, the name of the pin (in waveform window) starts from "pll: pll_inst1|locked" ... , not like "clk_divider: pll: pll: pll_inst1| locked" ....     Could this be the reason behind the error related to not finding the node in the design?   Thanks and regards, Kapil