Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How quartus duplicate registers by Synthesis Attributes (Verilog-2001)?

KTsan
Novice
1,703 Views

I am using Quartus Standard 16.1.

I have 5 modules like this:

 

top_mod

|--> mod1

|--> mod2

|--> mod3

|--> mod4

 

All of them are sharing the same clock and reset signals.

 

By using timing closure tool, it is highlighted that some registers in mod1, mod2 and mod3 have high fan-out values resulting -ve slack value and fail to meet the timing requirement.

 

I tried to insert Synthesis Attribute (*maxfan=10*) to those highlighted registers. Some registers are show up in the "Registers Duplicated to Honor Maximum Fanout Requirement" report but not all of them.

 

It is found that the report is always show duplicated registers up to TEN (10) records only.

 

1) Is it the report problem? (that showing up only the top 10 records).

If it is the case, how to verify which registers are being duplicated?

2) or quartus will duplicated registers up to n registers only? how to hint quartus to duplicate more registers?

 

Regards,

Ken

 

 

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1 Reply
Kenny_Tan
Moderator
979 Views

Hi Ken,

 

There are some condition when you set the max fan out will limit those duplication of register. Needless to say, it will be better that you use coding to duplicate those register because you have much more control on the duplicated register that you want to fan out to.

 

For example, if you have a register A fan out 1000 to module A, ​100 to module B, 2000 to module C. seting the max fan out will not help you to drive the fan out base on those module, it will end up timing being worst. So, it will be better to use coding to control your fan out directed to.

 

Thanks

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