How should I write Verilog to describe DDR?

Altera_Forum · ‎09-17-2013

I have a design, which I need make the data is launched by double data rate (DDR). In this case, should I write the Verilog like this ? :

always @(posedge clk or negedge clk)

begin

output <= a;

end

Another approach I can think is I use PLL to create two clocks: clk1 and clk2. The period of clk2 is twice as clk1 while they have exactly same phase. Then, I use clk1 to launch data in SDR but output clk2 and data. Then the data with clk2 is DDR. But I don't think this is the right approach since this is actually still SDR.

Hope anyone has experience in this can give some advices.

Thanks very much.

Altera_Forum · ‎09-17-2013

The always block isn't synthesizable.

You'll use a altddio_out megafunction, it can't be inferred from HDL.

Altera_Forum · ‎09-17-2013

Just to clarify, one can describe synthesizable DDR I/O in Verilog but, as FvM said, Quartus won't infer it and won't use the DDR I/O logic embedded in the I/O elements.

So, you should use the altddio_out megafunction.

Altera_Forum · ‎09-18-2013

Thanks very much, both of you.