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Explain in detail steps.
below are steps are done
-
LIBRARY lpm;
USE lpm.lpm_components.all;
-
still error
Error (10346): VHDL error at lpm_inv_0.vhd(43): formal port or parameter "LPM_WIDTH" must have actual or default value
Error (10784): HDL error at lpm_pack.vhd(219): see declaration for object "LPM_WIDTH"
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Hi,
Please modify the symbol properties & compile again,
Right Click on symbol(LPM_DFF)-> properties-> Parameter as shown below,
if this has not resolved then provide bit more information like,
- Quartus edition(Lite/Pro/Std) & Version used
- Device part number used
- Elaborate about, what exactly you are trying?
Regards,
Vicky
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Hi,
Have you resolved the issue?
Should I consider that case to be closed?
Regards,
Vicky
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Hi,
Please refer the attached screenshot & try at your end.
please let me know if you have any different concern.
Regards,
Vicky
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Hi,
Symbol synthesis will work,
Can you try to convert the same symbol to VHDL and synthesis.
regards,
Balakrishna
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Hi Balakrishna,
After successfully synthesis(my last post) , instantiate it in top module like below,
- Open .bdf file
- File-> Create/Update->Create VHDL component declaration component files for current file(It will create .cmp file)
- Open that .cmp file & instantiate it in top module & then compile that top module.
Regards,
Vicky

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