Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to add Quartus constraints when using Intel AOC compiler




I want to create an FPGA accelerator using AOC. My design is eating up a lot of resources on chip and I got the following errors from Quartus:


Error (170011): Design contains 1925001 blocks of type combinational node.  However, the device contains only 1866240 blocks.
Warning (14714): The Fitter is having difficulty fitting the design.  Try increasing the "Auto Packed Register" setting under "Advanced Fitter Settings" to minimize area.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:37:31
Info (11888): Total time spent on timing analysis during Global Placement is 544.80 seconds.



After doing a bit research, I found out after calling aoc to compile my OpenCL kernel, there will be a QSF file (afu_opencl_kernel.qsf) generated under the build directory. And in this QSF files, I found that this flag (i.e., auto packed register) has a default value NORMAL. I want to change the default value NORMAL to "minimize area" and try to minimize the area. 

My question is: how should I tell Quartus/AOC that I want a specific flag for the `QII_AUTO_PACKED_REGISTERS` option?  Is there a way to pass the QSF constraints to AOC?

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