How do I connect my CDPLK pin to the GCLK without the use of a clock control block in quartus ?

[sgadco]

Hello,

I am using the Cyclone 10 LP and Quartus Prime Standard Edition 18.1. I am using the Y6 pin(CDPCLK) for my FPGA_CLK signal. This clock signal has to be given as an input to the PLL. Unfortunately, only dedicated clock signals can be given as input to PLL. I need the CDPLK pin to drive the Global Clock Network(GCLK). After reading the documents, I noticed that the clock control block cannot be used as it cannot drive the inputs to the PLL if the pin is a CDPCLK pin. Is there any way I can use a buffer similar to BUFG in Xilinx to connect my CDPCLK pin to the GCLK to drive the input of the PLL? I need to drive PLL and PLL outputs should be connected to the Global network

[GY_Intel]

Hi, Please refer to the similar thread. Thanks

[sgadco]

Hello,

Can you post the link to the thread. I am unable to find any similar thread. Thanks

[EngWei_O_Intel · Accepted solution]

Hi Aaron

You are right. Clock control blocks that have inputs driven by dual-purpose clock I/O pins are not able to drive PLL inputs, which is the behavior of the CDPCLK pin. The PLL IP will not be able to take the CDPCLK as reference clock. PLL should always take clock input pin or GCLK driven by clock input pin as reference clock.

Thanks.

Eng Wei