How to add constraint to Pll clk output

[Altera_Forum]

There are two clock sources whcih both generate from PLL in my design, inclk0 is 60MHz from input Pin, c0 is 100MHz and c1 is 160MHz. I only add a constraint to input clock(FMAX_REQUIREMENT "60 MHz"), Classic timing analyzer shows setup time violation in 100MHz and 160MHz, but all the warnings are about the configuration parameters before starting the main state machine in IP. There are always error bit in running but it is OK when i changed PLL to generate 50MHz and 80MHz clock, so how can i fix this problem? Should i add constraint to PLL output and how? 

Thanks a lot!

[Altera_Forum]

Simply assume, that the timing analyzer gets sufficient information about the PLL clocks from the PLL parameters (you can check this in the timing analyzer report). The problem is in the design itself, not the clock. You have to check the timing analyzer report in detail to understand the nature of the timing violation, e.g. if it's caused by a signal crossing the clock domains or if it's within a clock domain.

[Altera_Forum]

The bit error only occurs at 100MHz and 160MHz condition, if i change the configuration to 50MHz and 80MHz or delete some modules in design, the system is OK, so i don't think it is the problem in design. 

BTW, i use Stratix2 EP2S130F1020C5, the occupied resource is 20% Logic, 12% Register, 39% M512, 84% M4K, 33% MRAM and 19% DSP9x9. If i reduce the resource to 10% Logic, 10% Register, 39% M512, 10% M4K, 33% MRAM and 19% DSP9x9, system is OK.

[Altera_Forum]

--- Quote Start ---  i don't think it is the problem in design.  --- Quote End ---   Most timing violations disappear, if you reduce the clock frequency. It's also normal behaviour, that the timing depends on design place and route, so it's changed when you add or remove modules.  As said, you won't get far without understanding the nature of the timing violation.

[Altera_Forum]

I agree with this, now i want to find which pathes are critical to the error, but from timing analyzer report i can't find it and i analyze every violate signal. How can i add constraints to avoid the error or have any idea to locate the path? 

Thank you very much!

[Altera_Forum]

A clock constraint can only clarify an existing timing requirement to the timing analyzer. The fact, that a timing violation is reported for your design along with an actual design failure suggests that the timing analyzer is aware of the timing requirements, but timing closure can't be achieved. In this case, an additional timing constraint doesn't change anything. The best method is to change the critical pathes, e.g by adding pipeline registers. 

 Timing constraints are typically necessary for external signals, or to inform the timing analyzer, that the default assumptions are not valid for particular signals.  I understand from your post, that you are facing many timing violations with the fast clock settings. You may want to trace the top red lines from the report to understand, what's the basic problem.

[Altera_Forum]

As i mentioned before, the registers in IP are written in 100MHz clock, some of them are used in 160MHz, so the report shows timing violation but actually they won't lead system error. The timing violations are also exist in 50MHz and 80MHz design. Anyway, I will read all violation messages one by one.