How to give a multicycle set up constraint in the time quest timing analyzer.

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How to give a multicycle set up constraint in the time quest timing analyzer.

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Hi all,

I am using galois field multiplier in my design. I want to give this multiplier path a multi cyle path. For single bit I know how to give this constraint.But how to give the constraint when there are more then one bit is there.For example

reg1 and reg2 are two input register.Both registers are 13 bits long.And reg3 is output register which is also a 13 bit register.Now when I am checking without giving any constraint to my design, I am getting hell number of critical path between either reg1 and reg3 or reg2 and reg3 for different bit.i.e I am getting critical path between reg1[5] and reg3[1],reg2[2] and reg3[6] .......

I want to know that is there any method to give the multi cycle path constraint between reg1 and reg3 and same way between reg2 and reg3?

Thanks in advance,

Regards,

Krupesh.

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