How to assign LVDS emulated pins on Cyclone V

[Altera_Forum]

I am trying to assign LVDS emulated pins to outputs of my top level design. 

I am using an ALTLVDS_TX component to be able to send my outputs in LVDS format. In the Assignment Editor, I assign pins like this: LVDS_LCD_CAM_3_P Location PIN_E11 LVDS_LCD_CAM_2_P Location PIN_W21 LVDS_LCD_CAM_1_P Location PIN_Y24 LVDS_LCD_CAM_0_P Location PIN_AA20 LVDS_LCD_CAM_CLK_P Location PIN_D12 LVDS_LCD_CAM_CLK_P I/O Standard LVDS_E_1R LVDS_LCD_CAM_3_P I/O Standard LVDS_E_1R LVDS_LCD_CAM_2_P I/O Standard LVDS_E_1R LVDS_LCD_CAM_1_P I/O Standard LVDS_E_1R LVDS_LCD_CAM_0_P I/O Standard LVDS_E_1R  I checked in the Pin Planner that the negative pin is associated to the respective positive one. When I compile the design, the Fitter stops and writing this message:  "Error (14566): Could not place 3 periphery component(s) due to conflicts with existing constraints (3 pin(s))"  "Error (175020): Illegal constraint of pin to the region (89, 18) to (89, 25): no valid locations in region"      What do I have to configure to get the fitter to place the outputs on the LVDS pins?  Regards,  Philippe

[Altera_Forum]

Are three of those pins in a bank with other I/O operating at a different voltage? Ensure all the I/O in the bank you're constraining your I/O to are 2.5V compatible. 

 Which device is it and which bank are you targeting? Are you targeting a bank that features true LVDS drives? I suspect you can place emulated LVDS drivers in these banks, but it's worth checking.  If you remove all your I/O placement, does Quartus fit it? Always worth trying as a sanity check.  Cheers, Alex

[Altera_Forum]

Hi Alex, 

 I solved the problem using two different ALTLVDS_TX. Using only one, you have to get all the outputs assigned on the same edge of the device. Unfortunately, the board is already finished and outputs can't be moved. We have two outputs on the TOP edge and three on the RIGHT edge.  At least now the design fit the fpga.  Thank you for the reply.  Regards, Philippe