How to bind pins for P tile PCIe

[GDeXi]

P tile Avalon-ST for PCIe IP Core have both rx_n_in and rx_p_in . Before, the binding difference should be taught to have only one pin . Now I confuse how to binding it.

 ,input  wire          rx_n_in0 

     ,input  wire          rx_n_in1 

     ,input  wire          rx_n_in2 

     ,input  wire          rx_n_in3 

     ,input  wire          rx_n_in4 

     ,input  wire          rx_n_in5 

     ,input  wire          rx_n_in6 

     ,input  wire          rx_n_in7 

     ,input  wire          rx_n_in8 

     ,input  wire          rx_n_in9 

     ,input  wire          rx_n_in10

     ,input  wire          rx_n_in11

     ,input  wire          rx_n_in12

     ,input  wire          rx_n_in13

     ,input  wire          rx_n_in14

     ,input  wire          rx_n_in15

     ,input  wire          rx_p_in0 

     ,input  wire          rx_p_in1 

     ,input  wire          rx_p_in2 

     ,input  wire          rx_p_in3 

     ,input  wire          rx_p_in4 

     ,input  wire          rx_p_in5 

     ,input  wire          rx_p_in6 

     ,input  wire          rx_p_in7 

     ,input  wire          rx_p_in8 

     ,input  wire          rx_p_in9 

     ,input  wire          rx_p_in10

     ,input  wire          rx_p_in11

     ,input  wire          rx_p_in12

     ,input  wire          rx_p_in13

     ,input  wire          rx_p_in14

     ,input  wire          rx_p_in15

     ,input  wire          tx_n_out0

     ,input  wire          tx_n_out1

     ,input  wire          tx_n_out2

     ,input  wire          tx_n_out3

     ,input  wire          tx_n_out4

     ,input  wire          tx_n_out5

     ,input  wire          tx_n_out6

     ,input  wire          tx_n_out7

     ,input  wire          tx_n_out8

     ,input  wire          tx_n_out9

     ,input  wire          tx_n_out10

     ,input  wire          tx_n_out11

     ,input  wire          tx_n_out12

     ,input  wire          tx_n_out13

     ,input  wire          tx_n_out14

     ,input  wire          tx_n_out15

     ,input  wire          tx_p_out0

     ,input  wire          tx_p_out1

     ,input  wire          tx_p_out2

     ,input  wire          tx_p_out3

     ,input  wire          tx_p_out4

     ,input  wire          tx_p_out5

     ,input  wire          tx_p_out6

     ,input  wire          tx_p_out7

     ,input  wire          tx_p_out8

     ,input  wire          tx_p_out9

     ,input  wire          tx_p_out10

     ,input  wire          tx_p_out11

     ,input  wire          tx_p_out12

     ,input  wire          tx_p_out13

     ,input  wire          tx_p_out14

     ,input  wire          tx_p_out15

Thanks a lot !!

[BoonT_Intel]

Hello Sir,

The serial output and serial input always some with differential pin. So, they should have "P" and "N" pins. For PCIe IP before P-tiles, the "N" pin is not generate at the PCIe IP top level. However, if you run full compilation. You can see fitter auto assign the "N" pin appended with (n) . You can find this info in the fitter report, under resource section, output/input pins. below is the screenshot for non-ptile PCIe fitter report.

For P-tile, the "P" and "N" pins is declare at the PCIe IP top level, what you need to do is pull both "P" and "N" signal to your design top level. And you only need to take care about the "P" pin location like what you did for non-Ptile PCIe, then quartus will auto fit the "N" pin for you.

[GDeXi]

Thanks , thanks very much, I have figure it out.

I was so stupid that I asked you this question, which brought you trouble.

[BoonT_Intel]

No problem 😄 Hope my answer here can help others user as well.