How to check signal waveform.

[Altera_Forum]

I have this VHDL code within my architecture: 

 architecture first of butterfly8 is  signal butterfly8_r_Z1, butterfly8_r_Z2, butterfly8_r_Z3, butterfly8_r_Z4: std_logic_vector(31 downto 0);     I know that I can use Vector Waveform File to monitor my waveform of INPUT and OUTPUT pins. Would it be possible to monitor my signal, such as butterfly8_r_Z1 in the architecture? If so, how to do it? Thanks

[Altera_Forum]

Synthesize the design. In the .vwf Insert Node or Bus, and then locate that signal. Note that it you're doing a timing simulation, i.e. the design has been synthesized, then a lot of signals get synthesized away. That's not to say they're removed, they just don't exist as a point you can "see". For example, if your signal was between two AND gates, then they might get merged into a single LUT, and the actual signal doesn't exist, but the behavior of the two AND gates does. If it's a register, then you should be in good shape.  

I would recommend just doing a functional simulation. This can be chosen in Assignments -> Settings -> Simulation. Be sure to read the Quartus II handbook on simulations: http://www.altera.com/literature/hb/qts/qts_qii53017.pdf

[Altera_Forum]

What should I select in the FILTER? For input and output pins, it is normally PINS:ALL. What about for the signal within architecture?

[Altera_Forum]

For example, I have a simple code: 

 Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity orgate2 is port(  out1 : out std_logic_vector(3 downto 0) ); end orgate2; architecture add of orgate2 is signal temp : std_logic_vector (3 downto 0);  begin  temp <= "1111";  out1 <= temp - "1100"; end add;   I want to check the signal temp. Then, I go to node finder and select design entry (all names). On the list, I have selected the node temp. Now, the temp node is on my waveform list and I would like to perform simulation. However, when I performed the simulation, the temp node no longer exist and gone. Anyone can help?

[Altera_Forum]

First you're probably doing a timing simulation, which means it's after synthesis, so temp would no exist because it gets synthesized out. 

Second, even if doing a functional simulation, temp isn't doing anything. Your simulating 1111 - 1100. That is a constant. Note that this is not sequential code but parallel, so all things are happening at once. Basically the code will have a constant output of out1 getting 0011. There's no logic in the design.

[Altera_Forum]

For functional sims, use pre-synthesis. For timing use post-fit. THe other ones work too. For example, if you choose post-fit and select a register, and that node name exists in the pre-synthesis, it will use it in the functional simulation. Worst thing that happens is you choose a node that doesn't exist in your simulation and have to go back and find one that does. You'll quickly get an understanding of what's available.

[Altera_Forum]

I am using Functional Simulation. Sorry, I am quite new so couldn't really understand. Would you mind to give a simple exampe. So that I can check my temp node?

[Altera_Forum]

temp is a constant, so there's no point in "checking it". It will always be removed during synthesis since it doesn't do anything. I really don't know what you're trying to do, but would suggest getting a book on HDL design. Probably the best thing when getting started is to think in terms of schematics, not code. If you have a constant in a schematic that subtracts another constant, the result is a constant. 

(And as I said, this isn't sequential, where temp gets a value first. You could switch the order of these two statements and it's the same thing. )

[Altera_Forum]

I got what you mean and that was just a simple example.  

 Actually, I want to check the waveform of a signal declared within the architecture.   I am actually designing a system where there are too many input and output ports. Therefore, I am thinking to move all my input and output ports within the architecture. Note that, I don't have to implement this to hardware but I would like to try it and run using VHDL. So, what I am actually doing is setting the input as constant. For the output, I would like to check the signal waveform. Thats why I want to do such an operation. Could you suggest some methods to do this?

[Altera_Forum]

cwjcwjcwj, 

 You can use the Vector Waveform to do that checking, but it is normally used to check (functional or timing simulation) sequential behaviours, not just combinational. However, to check the output signal, you must to add to your Vector Waveform file the inputs and output of your architecture.   To add those inputs/outputs (or signals) do: Edit -> Insert -> Insert Node or Bus  after, just choose the pins as Rysc has already said.  You must to set the configuration of your input and after save the file. Make the compilation and then verify the output pins.  My best, higor

[Altera_Forum]

Thanks, Higor.  

 I am actually writing VHDL for 128 points FFT and I am using floating point (32 bits precision). So, I need 128*32 pins for inputs and 128*32 pins for outputs. I am sure none of the existing device supports so many pins. I believe there are many ways to solve it. Maybe Parellel to Serial converter. What if I am writing a test bench? Any comments and suggestions?

[Altera_Forum]

use virtual pins. goto Assignments => Assignment Editor, put Virtual Pin into the Assignment Name column, change the value to On, make sure Enabled is set to Yes, and select the nodes to apply this to. You can use wildcards in the To column.

[Altera_Forum]

I have assigned all my input and output pins of FFT to VIRTUAL PINS. However, when I compiled it, it still telling me I have insufficient pins. Anyone know why?

[Altera_Forum]

--- Quote Start ---  Thanks, Higor.    I am actually writing VHDL for 128 points FFT and I am using floating point (32 bits precision). So, I need 128*32 pins for inputs and 128*32 pins for outputs. I am sure none of the existing device supports so many pins. I believe there are many ways to solve it. Maybe Parellel to Serial converter. What if I am writing a test bench? Any comments and suggestions?  --- Quote End ---     I am afraid you are on the wrong path... data processing can't be done that way. Your input need to be 32 bits(possibly 16 bit real, 16 bit imag) and so your output.   The fft points of 128 or 1024 ...etc are never meant to be entered all in parallel. The fft nees to wait until all points are ready then it starts processing to produce an output.

[Altera_Forum]

Thx, KAZ. Do you mean I need something like parallel to serial converter (to convert the 128 input points from P to S). Then, wait (store in memory) until 128 points available and start the FFT process. Is this going to be a problem with the latency or delay?

[Altera_Forum]

I don't see why you need to do par/ser conversion. I can assume your input isn't that wide e.g. it could be ADC output with finite bitwidth. 

If you are using altera fft then it will do the job of waiting for you. So all you have to do is to input to your fft the correct set of inputs then read the output.   Normally fft will output one block late(receive time + processing time), this shouldn't matter. I don't know of any fft that can output straightaway because it needs to have all points ready first. each ouput point is eventually computed from the scaled sum of products of all input points.   Since you are a beginner I don't see why you use floating point. You better use fixed point(2's complement) and 16 bit real/imag is adequate for the most demanding applications.

[Altera_Forum]

I am actually writing my own FFT module in which is 128-points FFT size. I am using floating-point as I have found the library in Quartus II. Are there any libraries for fixed-point implementation? 

 By the way, what if I have a VHDL design that I want to use as a component. And this VHDL design has many I/O ports as well. What is the best way to perform compilation and simulation? Is it using Virtual Pins as mentioned by thepancake?

[Altera_Forum]

use numeric_std library. 

use singed type in your vhdl code (and use std_logic at io), you can easily cast or convert between these two types. Do your internal computation all in signed.   use 16 bit real and 16 bit imag. In your case you must have adequate storage for your fft points per computation. I don't know details of the fast fourier computation technology but I know it splits up the full set of points into smaller sets, unlike traditional DFT which used to deal with the whole vector. You will need loads of multipliers and adders in all cases.   Therefore, you don't need to think of virtual pins. I wouldn't care about it for now. It is used occasionally as explained by the pancake.

[Altera_Forum]

Thanks. Yes, I splits the FFT up into smaller sets (the butterfly computation). And each of these smaller sets, I write a VHDL code and treat it as a component and call it in my high-level design. What if I am writing a low-level VHDL code (which I will use it as a component of my FFT) and it has many I/P ports, and I would like to perform a small simulation? Should I also use the way you mentioned?  

 One more last question: If say I am using 128-point FFT. Is it the 128 real and imaginary inputs will take turn to input to the device using 16 bits real and 16 bits imag input pins?

[Altera_Forum]

For simulation, yes use virtual pins to tell quartus not to bother about them or you can use other logic tricks to remove some of your io. 

 The 128 pairs will come in successively. real and imaginary are better fed in parallel(not interleaved).

[Altera_Forum]

Thank you so much all! Since I just want to perform simulation (for smaller sets), I will use the virtual pins to perform simulation. 

 However, for the high-level, I will use the method suggested by KAZ where only 16-bit for real and 16-bit for imag are use. And the 128 inputs take turns to input to the device.  But, why even I have assigned all the I/O pins as virtual pins, the message of 'can't place pins due to device constraints' still pop up? Any suggestions? I have checked with the Pin Planner and all the I/O pins gone. So, I am quite sure I have assigned the virtual pins properly.