How to constrain Async SRAM Interface

[Altera_Forum]

What is the proper way to constrain an asynchronous SRAM interface? I've already looked at the Async SRAM thread (http://alteraforum.org/forum/showthread.php?t=3423) so please don't point me there. 

 Below are the constraints that I've generated from the notes in the above link.  # Address (ADDR) trace delay from FPGA to SRAM set tADDRtr_max 1.5 set tADDRtr_min 1.0 # ADDR to DATA access time set tAVQV_max 10.0 set tAVQV_min 10.0 # Chip Enable (CE) trace delay from FPGA to SRAM set tCEtr_max 1.5 set tCEtr_min 1.0 # CE to DATA access time set tCEQV_max 10.0 set tCEQV_min 10.0 # Output Enable (OE) trace delay from FPGA to SRAM set tOEtr_max 1.5 set tOEtr_min 1.0 # OE to DATA access time set tOEQV_max 6.5 set tOEQV_min 6.5 # Data (DATA) trace delay from the FPGA to the SRAM set tDATAtr_max 1.5 set tDATAtr_min 1.0 # Constrain the read timing with respect to the address bus. for {set i 0} {$i < 20} {incr i} { # Create a clock on each output port of the address bus (addr) create_generated_clock -name "o_SRAM_Addr_bit${i}_clk" -source }] "] } for {set i 0} {$i < 16} {incr i} { # Constrain the input timing with respect to each address bit. set_input_delay -max -clock "o_SRAM_Addr_bit${i}_clk" -add_delay }] set_input_delay -min -clock "o_SRAM_Addr_bit${i}_clk" -add_delay }] } # Constrain the read timing with respect to the output enable (rd) create_generated_clock -name {oe_clk} -source }] set_input_delay -max -clock {oe_clk} -add_delay }] set_input_delay -min -clock {oe_clk} -add_delay }] # Constrain the read timing with respect to the chip enable (ce) create_generated_clock -name {ce_clk} -source }] set_input_delay -max -clock {ce_clk} -add_delay }] set_input_delay -min -clock {ce_clk} -add_delay }]The clock source for the generated clocks (i.e. [get_pins {nes_pcb|clk_gen|pll_nes_sram_vid_CLKIN_50M_cyc4|altpll_component|auto_generated|pll1|clk[1]}]) is the same clock that is driving the o_SRAM_Addr/CS_n/OE_n signals. But I keep getting really weird warnings in Quartus when giving it the above constraints. I don't understand why it is saying there is no path between the clock source and o_SRAM_Addr/CS_n/OE_n when that same clock source is what is driving those o_SRAM_* outputs.  Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit0_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit1_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit2_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit3_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit4_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit5_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit6_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit7_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit8_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit9_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit10_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit11_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit12_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit13_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit14_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit15_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit16_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit17_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit18_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_Addr" of clock "o_SRAM_Addr_bit19_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_OE_n" of clock "oe_clk" and its clock source. Assuming zero source clock latency. Warning (332088): No paths exist between clock target "o_SRAM_CS_n" of clock "ce_clk" and its clock source. Assuming zero source clock latency.Is there a better way to constrain the interface? Treating every address line and CS and OE signal as a clock seems a bit kludgy to me. There must be a better way... But if not, how can I get rid of all those warnings?  Thanks!!  Jonathon

[Altera_Forum]

This post has a document and project showing the method I used to determine SRAM constraints: 

 http://www.alteraforum.com/forum/showthread.php?t=31457  Cheers, Dave