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Altera_Forum
Honored Contributor I
1,208 Views

How to constrain HPS I2C Bus?

Hi 

 

My design uses a Cyclone 5 FPGA with an HPS that connects I2C Bus 1 SCL and SDA to external pins that connect to an RTC (Real Time Clock) chip with an I2C Bus interface. The HPS software can successfully read and write to the RTC chip so it does work. However I'm not sure how to constrain the I2C Bus in the sdc file and verify it in TimeQuest. 

 

I'm assuming I need to do at least two things: 

- use create_generated_clock to create an I2C Bus 1 clock (TimeQuest tells me that "RTC_SCL was determined to be a clock but was found without an associated clock assignment", and the Fitter tells me that "Register soc_system:u0|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|i2c1_inst~FF_3393 is being clocked by RTC_SCL" 

- set setup and hold limits for the RTC_SCL and RTC_SDA signals (which are connected to the FPGA I2C Bus SCL and SDA signals). This isn't a problem - I know what to do here 

 

My main problem is the create_generated_clock statement. I've tried using create_generated_clock as follows: 

create_generated_clock -name rtc_scl -source [get_ports -nocase {soc_system:u0|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|i2c1_inst_i2c1_inst_SCL[0]}] -divide_by 250 [get_ports RTC_SCL] 

 

But it fails with these error messages: 

Ignored filter: soc_system:u0|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|i2c1_inst_i2c1_inst_SCL[0] could not be matched with a port 

Ignored create_generated_clock: Argument -source is an empty collection 

 

I wondered if anyone could advise me on how to fix the -source path in create_generated_clock please?
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3 Replies
Altera_Forum
Honored Contributor I
152 Views

If someone has a solution, I am also interrested...

Altera_Forum
Honored Contributor I
152 Views

This is not really a solution, more of an observation. Given the ultra-slow nature of I2C (100Khz or 400Khz), constraining the timing seems superflous.

Altera_Forum
Honored Contributor I
152 Views

 

--- Quote Start ---  

 

My main problem is the create_generated_clock statement. I've tried using create_generated_clock as follows: 

create_generated_clock -name rtc_scl -source [get_ports -nocase {soc_system:u0|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|i2c1_inst_i2c1_inst_scl[0]}] -divide_by 250 [get_ports rtc_scl] 

 

But it fails with these error messages: 

Ignored filter: soc_system:u0|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|i2c1_inst_i2c1_inst_SCL[0] could not be matched with a port 

Ignored create_generated_clock: Argument -source is an empty collection 

 

I wondered if anyone could advise me on how to fix the -source path in create_generated_clock please? 

--- Quote End ---  

 

 

Well, the problem is as it says ... the argument you provide to get_ports in the -source parameter is not a valid port (and probably should not be a port at all). It should be some internal reference clock signal, or maybe [get_ports {clock_50}] or something like that.
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