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Altera_Forum
Honored Contributor I
980 Views

Ones counter using numeric_std inside process

 

 

 

 

 

I had an error while working on ones counter inside the process. I use numeric_std library. Here is the key part of the code. 

 

signal one_buf:unsigned(7downto0); 

signal out_buf:std_logic_vector(7downto0); 

counter_one:process(out_buf1) 

variable one_buf1 :unsigned(7downto0):=(others=>'0'); 

begin 

for i in 0 to 7 loop 

one_buf1 := one_buf1 +unsigned(out_buf(i)); 

endloop;  

one_buf <= one_buf1; 

end process counter_one; 

 

The error message is Error(10305) cannot convert type "std_ulogic" to type "UNSIGNED". I do not understand what is wrong here. 

Thanks in advance for the answers. 

 

 

 

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3 Replies
Altera_Forum
Honored Contributor I
50 Views

out_buf1(i) is a single bit. You need to make it into an array. something like: 

 

 

one_buf1 := one_buf1 + ("" & out_buf(i));
Altera_Forum
Honored Contributor I
50 Views

 

--- Quote Start ---  

out_buf1(i) is a single bit. You need to make it into an array. something like: 

 

 

one_buf1 := one_buf1 + ("" & out_buf(i)); 

--- Quote End ---  

 

 

 

Thanks for the answer, Tricky. 

 

I tried and then there are some other errors.  

 

Error (10327): VHDL error at mess_extractor.vhd(278): can't determine definition of operator ""&"" -- found 4 possible definitions 

Error (10647): VHDL type inferencing error at mess_extractor.vhd(278): type of expression is ambiguous - "std_ulogic_vector" or "std_logic_vector" are two possible matches 

 

Can you comment on this too? Thanks!
Altera_Forum
Honored Contributor I
50 Views

try this: 

 

one_buf1 := one_buf1 + unsigned'("" & out_buf(i))
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