Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to constrain Jtag signals of Cyclone 4 FPGA?

SK_VA
Beginner
1,156 Views

I constrained all I/Os of my FPGA Cyclone 4 device.

But still it shows unconstrained path for jtag signals:-

altera_reserved_tdi,altera_reserved_tdo,altera_reserved_tms,altera_reserved_tck.

Can I set Jtag signals as false path?

How to constrain these signals?

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3 Replies
Rahul_S_Intel1
Employee
207 Views

Hi ,

Those signals are reserved signals.

Rs

SK_VA
Beginner
207 Views

These are reserved signals.But Timing analysis shows unconstrained paths for these pins.

How to solve this?

Knug
Beginner
180 Views

Same question I have.

Timing STA analysis showed

  • no output delay : altera_reserved_tdo
  • no input delays : altera_reserved_tms, altera_reserved_tck & alrera_reserved_tdi

How do we constrain them ?

 

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