Hi All,
I am beginner to FPGA tools.
I need to extract the area and delay for a register.
module regr(
input A,
input CLR,
input SET,
input CLK,
output reg Z
);
always @(posedge CLK or negedge CLR or negedge SET) begin
if (!CLR) Z <= 1'B0;
else if (!SET) Z <= 1'B1;
else Z <= (A);
end
endmodule
As this register is part of a bigger project, I have set all input and output pins as virtual and set the CLK as Global clock.
I am using a 4ns clock.
Please let me know the way to constrain the input and outputs.
Option A:
create_clock -name clk -period 4.000 [get_ports CLK]
set_input_delay -clock clk 0.2 [all_inputs]
set_output_delay -clock clk 0.2 [all_outputs]
Option B
create_clock -name clk -period 4.000 [get_ports CLK]
set_max_delay -from [all_inputs] -to [all_clocks] 3.800
set_max_delay -to [all_outputs] -from [all_clocks] 3.800
Please let me know if option A or option B is correct way of constraining.
Regards,
Upadyaya
