Error in Asynchronous UART during Simulation

[Altera_Forum]

I am using ISE 14.3 and I have programmed the UART with the help of P.Chu's FPGA Prototyping in VHDL.I am a beginner on UART design using VHDL and I am doing this as a part of my project. 

I have no syntax errors in the implementation. But when I do the simulation I get the following errors: ERROR:HDLCompiler:104 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 26: Cannot find <spi_pkg> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:854 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 35: Unit <toplevel> ignored due to previous errors. ERROR:HDLCompiler:374 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 52: Entity <toplevel> is not yet compiled. ERROR:HDLCompiler:69 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 53: <std_logic> is not declared. ERROR:HDLCompiler:69 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 54: <std_logic> is not declared. ERROR:HDLCompiler:69 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 55: <std_logic_vector> is not declared. ERROR:HDLCompiler:69 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 56: <std_logic_vector> is not declared. ERROR:HDLCompiler:69 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 57: <std_logic> is not declared. ERROR:HDLCompiler:69 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 58: <std_logic> is not declared. ERROR:HDLCompiler:104 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 60: Cannot find <baudrategen_uart> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:104 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 63: Cannot find <rxd1> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:104 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 68: Cannot find <flag_bw> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:104 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 73: Cannot find <txdinterface> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:104 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 78: Cannot find <txd> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:69 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 84: <tx_fifo_not_empty> is not declared. ERROR:HDLCompiler:854 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 93: Unit <baudrategen_uart> ignored due to previous errors. ERROR:HDLCompiler:374 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 104: Entity <baudrategen_uart> is not yet compiled. ERROR:HDLCompiler:69 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 105: <unsigned> is not declared. ERROR:HDLCompiler:69 - "E:/Project ISE files/UARTfullsample29Jan/UARTfull.vhd" Line 106: <unsigned> is not declared.  Can someone help me with this?  Thank you. Regards, Lydia

[Altera_Forum]

I think, you need another forum for ISE.