How to constrain my project to deal with these red time issues?

[Altera_Forum]

Hello, dears: 

 I'm using LPM_DIVDER in my project. The system clock frequency is 100MHz. It seems i can get correct result from SignalTap as attached file (CubeEnergy and X_Exp are the inputs of divider, and quotient is the output of it). But there are many time issues about the divider from the compilation report. I reported top 10 path as attached file.   How can i do to deal with this "red" infos?

[Altera_Forum]

I attched the data path detail.

[Altera_Forum]

Can you add a register stage just before the divide function. I understand if some designs do not permit the added clock cycle, but it would most likely improve your timing behavior.

[Altera_Forum]

--- Quote Start ---  Can you add a register stage just before the divide function. I understand if some designs do not permit the added clock cycle, but it would most likely improve your timing behavior.  --- Quote End ---    Thanks for you reply!  I will try it. Currently, my divider's denominator is 16bits and numeritor is 24bits. If i change both to 9bits, the divider will work well. It seems that divider's performence will decrease along with the input bit width increase.