How to constraint design to meet Recovery Timing

[Altera_Forum]

Hi, 

 I have a Cyclone III FPGA design. Quartus II generates a few of Recovery Timing violations. The path info is posted here:  Info (332115): Report Timing: Found 1 recovery paths (1 violated). Worst case slack is -4.863 Info (332115): -to_clock [get_clocks {inst|the_ddr|ddr_controller_phy_inst|ddr_phy_inst|ddr_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[0]}] Info (332115): -recovery Info (332115): -stdout Info (332115): Path# 1: Recovery slack is -4.863 (VIOLATED) Info (332115): 2210.000 2210.000 latch edge time Info (332115): 2210.856 0.856 R clock network delay Info (332115): 2210.706 -0.150 clock uncertainty Info (332115): 2210.647 -0.059 uTsu CTIDSCCM:inst|ddr_clock_crossing:the_ddr_clock_crossing|ddr_clock_crossing_upstream_fifo:the_upstream_fifo|dcfifo:upstream_fifo|dcfifo_u1g1:auto_generated|altsyncram_di31:fifo_ram|q_b[1] Info (332115):  Info (332115): Data Arrival Time : 2212.521 Info (332115): Data Required Time : 2210.647 Info (332115): Slack : -1.874 (VIOLATED) Info (332115): 33.332 33.332 latch edge time Info (332115): 33.909 0.577 R clock network delay Info (332115): 34.236 0.327 clock pessimism Info (332115): 34.216 -0.020 clock uncertainty Info (332115): 34.234 0.018 uTsu CTIDSCCM:inst|peri_clock_crossing:the_peri_clock_crossing|peri_clock_crossing_downstream_fifo:the_downstream_fifo|dcfifo:downstream_fifo|dcfifo_euf1:auto_generated|rdemp_eq_comp_msb_aeb Info (332115):  Info (332115): Data Arrival Time : 34.855 Info (332115): Data Required Time : 34.234 Info (332115): Slack : -0.621 (VIOLATED) Info (332115): 30.066 30.066 latch edge time Info (332115): 30.466 0.400 R clock network delay Info (332115): 30.326 -0.140 clock uncertainty Info (332115): 30.279 -0.047 uTsu CTIDSCCM:inst|ddr_clock_crossing:the_ddr_clock_crossing|ddr_clock_crossing_downstream_fifo:the_downstream_fifo|dcfifo:downstream_fifo|dcfifo_tsf1:auto_generated|altsyncram_ji31:fifo_ram|q_b[30] Info (332115):  Info (332115): Data Arrival Time : 34.414 Info (332115): Data Required Time : 30.279 Info (332115): Slack : -4.135 (VIOLATED) Info (332115): 2210.000 2210.000 latch edge time Info (332115): 2210.927 0.927 R clock network delay Info (332115): 2210.777 -0.150 clock uncertainty Info (332115): 2210.730 -0.047 uTsu CTIDSCCM:inst|ddr_clock_crossing:the_ddr_clock_crossing|ddr_clock_crossing_upstream_fifo:the_upstream_fifo|dcfifo:upstream_fifo|dcfifo_u1g1:auto_generated|altsyncram_di31:fifo_ram|q_b[1] Info (332115):  Info (332115): Data Arrival Time : 2212.416 Info (332115): Data Required Time : 2210.730 Info (332115): Slack : -1.686 (VIOLATED) Info (332115): 33.332 33.332 latch edge time Info (332115): 34.028 0.696 R clock network delay Info (332115): 34.297 0.269 clock pessimism Info (332115): 34.277 -0.020 clock uncertainty Info (332115): 34.297 0.020 uTsu CTIDSCCM:inst|peri_clock_crossing:the_peri_clock_crossing|peri_clock_crossing_downstream_fifo:the_downstream_fifo|dcfifo:downstream_fifo|dcfifo_euf1:auto_generated|rdemp_eq_comp_msb_aeb Info (332115):  Info (332115): Data Arrival Time : 34.386 Info (332115): Data Required Time : 34.297 Info (332115): Slack : -0.089 (VIOLATED) Info (332115): 30.066 30.066 latch edge time Info (332115): 30.123 0.057 R clock network delay Info (332115): 29.983 -0.140 clock uncertainty Info (332115): 29.959 -0.024 uTsu CTIDSCCM:inst|ddr_clock_crossing:the_ddr_clock_crossing|ddr_clock_crossing_downstream_fifo:the_downstream_fifo|dcfifo:downstream_fifo|dcfifo_tsf1:auto_generated|altsyncram_ji31:fifo_ram|q_b[30] Info (332115):  Info (332115): Data Arrival Time : 32.377 Info (332115): Data Required Time : 29.959 Info (332115): Slack : -2.418 (VIOLATED) Info (332115): 2210.000 2210.000 latch edge time Info (332115): 2210.284 0.284 R clock network delay Info (332115): 2210.134 -0.150 clock uncertainty Info (332115): 2210.142 0.008 uTsu CTIDSCCM:inst|ddr_clock_crossing:the_ddr_clock_crossing|ddr_clock_crossing_upstream_fifo:the_upstream_fifo|dcfifo:upstream_fifo|dcfifo_u1g1:auto_generated|a_graycounter_i47:rdptr_g1p|counter5a2 Info (332115):  Info (332115): Data Arrival Time : 2211.008 Info (332115): Data Required Time : 2210.142 Info (332115): Slack : -0.866 (VIOLATED) Info (332115): 2240.000 2240.000 latch edge time Info (332115): 2240.682 0.682 R clock network delay Info (332115): 2240.822 0.140 clock uncertainty Info (332115): 2240.923 0.101 uTh CTIDSCCM:inst|ddr_clock_crossing:the_ddr_clock_crossing|ddr_clock_crossing_upstream_fifo:the_upstream_fifo|dcfifo:upstream_fifo|dcfifo_u1g1:auto_generated|altsyncram_di31:fifo_ram|ram_block11a1~portb_address_reg0 Info (332115):  Info (332115): Data Arrival Time : 2240.820 Info (332115): Data Required Time : 2240.923 Info (332115): Slack : -0.103 (VIOLATED)   It seems to me that all the paths violated are related to DDR mem. The design is based on standard Cyclone III neek. I have tried serveral variations, and with different Timing Analysis settings (as suggested by TQ advsier, and fourm's other leads, etc.) but all with similar violation warning. They might be on the false paths. But it is involved with DDR memory, I have no clues that those paths can be set to false paths. Whatelse can I do to constain my design to meet the timing requirements?   Thank you in advance, David

[Altera_Forum]

Did You add SDC file generated by DDR memory core? And did You run TCL generated by the same core?

[Altera_Forum]

Analyze in TimeQuest, as it gives more information. Is the source register in the DDR controller, or is it something generated outside of the DDR megafunction and driving in? Is it crossing clock domains? (I think it may be, but not sure). I'm guessing this is a false path, but not quite enough info.

[Altera_Forum]

Thank you for yuor promptly reply. The SDC file generated by DDR memory core is in. I did not run TCL manually. I'm busy working on prototype board testing etc. I have to postpone this issue.  

 david