How to create a hard macro

Altera_Forum · ‎08-12-2010

Hi all

I need to turn my design into a hard macro. I could not figure out how to create a hard macro in Quartus ii. Could you please help me?

Altera_Forum · ‎08-13-2010

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Hi all

I need to turn my design into a hard macro. I could not figure out how to create a hard macro in Quartus ii. Could you please help me?

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Hi,

what do you mean with "Hard Macro" ? That the design is loaded in the FPGA at power up or preserving your P&R results for further use in other projects ?

Kind regards

GPK

Altera_Forum · ‎08-13-2010

You probably want to look into partitions. They can be exported/imported into projects and preserve placement and routing. Note that they can't be stamped out though, i.e. you have to import it into the same device and the same location.

Why do you need this?

Altera_Forum · ‎08-13-2010

my design consists of several similar components. I need to have exactly the same routing for all of the components.

What I want to do is to make one of the components as a hard macro, and then copy the hard macro to make the other components. (So, the components are not placed in the same locations but they have the same routing)

I have reviewed the documnet

"quartus ii incremental compilation for hierarchical and team-based design"

. I am not sure if I should follow hard-wired macros (page 37) or logiclock regions (page 45) or something esle?

Altera_Forum · ‎08-15-2010

Hi Mariam,

Altera devices do not have perfectly regular routing, so it would be very difficult to reproduce exactly the same routing in one part of the chip in another part. This is in addition to the fact that some columns have MLABs, MACs or RAMs instead of normal logic, so if any components are duplicated side-by-side, they may not even be able to reuse the same placement, let alone routing.

Why do you need the routing to be identical? The standard way to work is to set the same timing constraints (using SDC files) on the different components so that they're all optimized to the same extent.

Cheers,

Adrian Ludwin

Altera Corp

Altera_Forum · ‎08-17-2010

Thank you for your responses.

What if I make several logiclock regions (at the top level design) and import a same design partition (which is already complied, placed, and routed) into all these logiclock regions? Will all those regions have the same routing as the imported design?

I need to have identical routing, because I want to miniminze (as much as possible) the delay variations associted with routing and concentrate on other sources of delay.

Altera_Forum · ‎08-18-2010

I don't know the internals of Quartus, but I'm guessing that the design partition when imported will try to occupy the exact same space, and can't be moved just like that.

I don't get it... If your design is properly constrained, you don't have to worry about delay variations.