system verilog in Quartus

Altera_Forum · ‎08-17-2010

I can't understand system verilog.

I'm make two interfaces:


typedef struct {
        logic  dma_start;
        logic  dma_end;
        logic  dma_status;
        logic  dma_ctrl;
}dma_rx_t;
interface regs_if;
        dma_rx_t dma0_rx;
endinterface
interface pcie_rx_if;
   logic       rx_ack  ;
   wire       rx_ws   ;
   wire        rx_req ;
   wire rx_desc ;
   wire rx_data ;
   wire  rx_be;
   wire        rx_dv   ;
   wire        rx_dfr  ;
endinterface

make my module:


module artem_memio_if (
        input bit clk,
        input bit rstn,
        regs_if regs,
        pcie_rx_if pcie_rx
        );
(* keep = 1 *) wire rx_bar_hit_n;
assign rx_bar_hit_n = (pcie_rx.rx_desc | pcie_rx.rx_desc) ? 1'b1 : 1'b0;

upper level module:


module altpcierd_cdma_app_icm
(
…..
input rx_desc0 ,
…
);
regs_if regs();
pcie_rx_if pcie_memio_rx();
assign pcie_memio_rx.rx_req = rx_req0;
assign pcie_memio_rx.rx_desc = rx_desc0;
assign pcie_memio_rx.rx_data = rx_data0;
assign pcie_memio_rx.rx_desc = rx_desc0;
assign pcie_memio_rx.rx_dv   = rx_dv0;
assign pcie_memio_rx.rx_dfr   = rx_dfr0;
artem_memio_if artem_memio(
        .clk(clk_in),
        .rstn(rstn),
        .regs(regs),
        .pcie_rx(pcie_memio_rx)
        );

But quartus say:

--- Quote Start ---

Error: Net "top_example_chaining_pipen1b:core|altpcierd_example_app_chaining:app|altpcierd_cdma_app_icm:chaining_dma_arb|pcie_memio_rx.rx_desc[129]", which fans out to "top_example_chaining_pipen1b:core|altpcierd_example_app_chaining:app|altpcierd_cdma_app_icm:chaining_dma_arb|pcie_rx_if:pcie_memio_rx|pcie_rx_if.rx_desc[129]", cannot be assigned more than one value

Error: Net is fed by "top_example_chaining_pipen1b:core|altpcierd_example_app_chaining:app|altpcierd_cdma_app_icm:chaining_dma_arb|pcie_memio_rx.rx_desc[129]"

Error: Net is fed by "top_example_chaining_pipen1b:core|altpcierd_example_app_chaining:app|altpcierd_cdma_app_icm:chaining_dma_arb|pcie_rx_if:pcie_memio_rx|pcie_rx_if.rx_desc[129]"

Error: Net is fed by "top_example_chaining_pipen1b:core|altpcierd_example_app_chaining:app|altpcierd_cdma_app_icm:chaining_dma_arb|artem_memio_if:artem_memio|pcie_rx.rx_desc[129]

--- Quote End ---

Altera_Forum · ‎08-17-2010

i don't know System Verilog, but have you tried loading the same HDL in ModelSim to see if there is a discrepancy in tool behavior?