How to deal with on chip memory timing?

[Altera_Forum]

I want to make a fsm on an altera FPGA which uses on-chip memory. 

I want to take an input, get data from memory based on input, use that data in the next cycle. and so on. What is a good way to write verilog code for this while keeping timing in mind?

[Altera_Forum]

There's no special advice, just follow the HDL guidelines for RAM inferral. 

The on-chip RAM blocks are capable of operating at the chip's maximum clock frequency, so they're very unlikely to be the bottleneck in your design.