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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to define a signal as a clock

Altera_Forum
Honored Contributor II
‎04-20-2010 03:32 AM
2,157 Views

Hi, 

 

I'm interfacing an 8032 to an acek1k FPGA and compilation warns of my wr,ale,and G_clk (crystal input) as undefined clocks. I'm using schematic capture for design entry. How do I define these signals as clocks in Quartus II to get rid of the warnings? I'm not sure if it causing timing issues or not. 

 

TIA, 

Vic
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Altera_Forum
Honored Contributor II
‎04-20-2010 04:57 AM
1,262 Views

You can specify these pins as individual clocks in the classical timing analyzer setup. But the "timing issues" question can't answered easily because it depends also on the relation of these clocks in your design.

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