Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16593 Discussions

How to define clock while using flip flop

Altera_Forum
Honored Contributor II
‎04-28-2013 03:13 PM
977 Views

I am new to VHDL and i am facing one problem while writing a code. In my circuit i have different components like half adder, and gate and flip flop. When i perform the check syntax, i receive an error that clock is not defined. Attached is my code, please have a look on it and let me know my mistake. I know this question might looks stupid to some of you but as i am beginner so i would appreciate your feedback.  

 

Thanks, 

Syed Irtaza Haider
Preview file
3 KB
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎04-28-2013 04:20 PM
270 Views

The clue is in the error. In the "top" entity, you havent defined a clock signal or port.

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎04-29-2013 07:05 PM
270 Views

Thanks alot. i got your point. :) stay blessed

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.