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How to define clock while using flip flop

Altera_Forum
Honored Contributor II
‎04-28-2013 03:13 PM
1,206 Views

I am new to VHDL and i am facing one problem while writing a code. In my circuit i have different components like half adder, and gate and flip flop. When i perform the check syntax, i receive an error that clock is not defined. Attached is my code, please have a look on it and let me know my mistake. I know this question might looks stupid to some of you but as i am beginner so i would appreciate your feedback.  

 

Thanks, 

Syed Irtaza Haider
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Altera_Forum
Honored Contributor II
‎04-28-2013 04:20 PM
499 Views

The clue is in the error. In the "top" entity, you havent defined a clock signal or port.

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Altera_Forum
Honored Contributor II
‎04-29-2013 07:05 PM
499 Views

Thanks alot. i got your point. :) stay blessed

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