How to design divider circuit data path unit in Quartus II?

[Sabrina23]

Hi I'm having problem to design divider circuit using Quartus II Lite using schematic design. Most of the data path unit design I found only in VHDL code. But, I am required to design in schematic diagram for my assignment. Can anyone help me for the connection. I already have few modules such as shift left register, full adder, full substractor, accumulator, comparator, and data register. Do I need more modules? I hope there are some that experts on this can help me. 

[FvM]

Hi,

are you attending a "last century design methods" course? Schematic entry is legacy in Quartus, still supported but with shrinking functionality. If ever possible, I'd implement the divider in HDL. It can be still instantiated as schematic block if necessary.

What kind of divider are you designing? Fully parallel (like Quartus lpm_divide) or sequential (one or multiple result bits calculated per clock cycle)?

Regards

Frank

[Sabrina23]

Hi, currently I attending "Digital System" course. My divider type is the non-restoring divider. I found some in VHDL code but not sure if it can be instantiated as schematic block, since the schematic diagram is required for my assignment. Thank you.

Regards,

Sabrina

[FvM]

Hi,
the answer really depends on your exercise problem specification. If you are required to make a schematic (basically a structural design) comprised of elementary logic elements only, then have to build it from the scratch. The HDL code or a flow diagram of non-restoring algorithm can be used as a template.

A relative compact Verilog implementation copied from Stratix Cookbook is appended below. Question is which elementary logic/arithmetic functions are taken as granted and which have to be designed by yourself? 

Regards
Frank 

[RichardTanSY_Intel]

You can try to convert the HDL file to .bdf file. (only available in Quartus Standard/Lite, discontinued in Pro)

Once you have run "Analysis & Synthesis", click right the HDL file > Create Symbol Files for Current File.

I agreed with FvM, schematic can be visual friendly for smaller designs, but it comes with significant drawbacks as designs get more complex.

It is harder to manage large and complex circuits in schematic, it is not modular/parametrized (making design reuse challenging), and may not integrate well with other tools.

I know this is probably a one-time use for your assignment, but I recommend transitioning to a hardware description language such as Verilog or VHDL in future. 

Regards,

Richard Tan

[RichardTanSY_Intel]

Dropping a note to ask if my last reply was helpful to you.

Do you need any further assistance from my side?

Regards,

Richard Tan

[RichardTanSY_Intel]

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