How to dynamically adjust PLL phase

[Altera_Forum]

Hi, 

 I am using Quartus 7.2 SP1. I am currently trying to implement a reconfigurable PLL for debug purposes. I am using an367 (http://www.altera.com/literature/an/an367.pdf) as a reference. I want to put all the initial parameters of my PLL in a .mif file that I can use as an initialization file for the altpll_reconfig that I am using. Then using an In-System probe, I want to dynamically change the phases of my PLL.   Does anybody know if such a sample design already exists so that I don't have to reinvent it?  Thanks

[Altera_Forum]

I don't know of a sample design, but I did reconfigurable PLL's in a data product using a 2S60. It works fine. The only trouble I had was a year ago Altera updated how they handle reset. On the latest software, you will be fine.

[Altera_Forum]

The document you're using talks about 3 reference designs at the end, which you should be able to download from the same place you downloaded the AN367 document. The second one should be the one you're looking for. 

 Beware in reconfiguring though. Making changes to anything other than the post-scale counter or the phase will result in a PLL loss. That's what I'm currently trying to figure out is how to reacquire the lock. Perhaps someone will have an answer for that.

[Altera_Forum]

I use a 4 MHz reconfig clock. Upon the final reconfig pulse or a loss of lock, I hold the PLL in reset for 512 clocks. I don't just nudge the phase. My application is to change the fundamental clock rate. So, reset makes sense. I seem to recall I originally tried to run closer to the rated speed of the reconfig, but backed off to 4 MHz for timing reasons that were not well documented/reported. Again, this was with an older rev. of Quartus.

[Altera_Forum]

I finally figured out what was happening with my problem, and since this seems to be a thread on PLL reconfiguration problems, I thought I'd share what I learned. I only had to search through 3 documents and 1 troubleshooter to get all the information needed. So perhaps this will help someone in the future. 

 Formula's F(ref) = F(in) / N F(vco) = F(ref) * M = F(in) * M/N F(out) = F(vco) / C = (F(ref) * M) / C = (F(in) * M) / (N * C)  F(vco) = VCO frequency F(in) = input frequency F(ref) = reference frequency F(out) = output frequency M = multiplication counter N = division counter C = post-scale counter = up time + down time  A few things to consider F(vco)min * M/N < F(in) < F(vco)max * M/N  This is actually the one that got me. A functional simulation will not catch this error, only a timing simulation. The value of F(vco) min and max can be found in the corresponding Manual for the chip family you are working with. For the Stratix II (speed -3 and -4), they are: F(vco)min = 300MHz and F(vco)max = 1040MHz.  Therefore, since I was using a 50MHz input clock, my minimum M/N ratio has to be 6/1. I had it set to M = 5 and N = 1, hence my problem. The maximum is ~ 20/1. So check the documentation on the part you are using, as that is the only place I've found actual values for F(vco) min and max.  Also, if you don't already know, changes in C do not affect the PLL lock, only changes in M and N (don't quote me on the changing of phase, as I haven't messed with that, perhaps someone else can provide info on that). Therefore, if you change N or M, you are going to lose lock on your input clock for a period of time. The bandwidth setting that you use should affect exactly how quick the PLL responds and regains the lock. This being the case, you'll probably want to make sure you connect to the lock output of the PLL and check it before assuming that a reconfiguration when through (I'm sure this is a no-brainer, but it never hurts to remind).  The Implementing PLL Reconfiguration in **** document should contain all the information you need on the possible values of M, N, C, and all other variables. Be sure to use the correct document for the family of part you are using.  I think that's all I have for now. If you disagree with anything I've posted, please let me know and post your information. Otherwise, I hope this will be useful to someone and they won't have to spend the 2 1/2 days I did figuring out how things work and why they don't work. :)