How to enable Timing-driven compilation

[Altera_Forum]

Hi, 

 When I compile my project, I got a warning as below,   --- Quote Start ---  Warning: Timing-driven compilation is disabled - timing performance will not be optimized  --- Quote End ---    I checked the setting file. I assume settings about timing are set to ON.   I wonder do I make some mistake with .qsf file?  Regards, Clairlyn  Some sections of my .qsf: # Classic Timing Assignments # ========================== set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON # Analysis & Synthesis Assignments # ================================ set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name REMOVE_DUPLICATE_LOGIC OFF set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name SAFE_STATE_MACHINE ON set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON # Fitter Assignments # ================== set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS set_global_assignment -name SEED 3 set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE NORMAL set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON set_global_assignment -name ECO_OPTIMIZE_TIMING ON set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON

[Altera_Forum]

You need to compile your sdc in Time Quest Analyzer. Then the synthesis will be sdc driven.

[Altera_Forum]

--- Quote Start ---  You need to compile your sdc in Time Quest Analyzer. Then the synthesis will be sdc driven.  --- Quote End ---    I saved constraints to .sdc File in TimeQuest Analyzer, and added the .sdc to my project. After doing this, run a full compilation.  Are my steps correct? thx

[Altera_Forum]

You need to add this to your .qsf file for timing-driven fitting: 

 set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL NORMAL  Also, if you want synthesis to be timing-driven, add this also:  set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON  There are check boxes for both of these settings in the Settings dialog box.

[Altera_Forum]

After adding ROUTER_TIMING_OPTIMIZATION_LEVEL NORMAL to my .qsf file, it's done. 

 I really appreciate your help.  I wonder if quartus wouldn't optimize router timing without this line in .qsf file?

[Altera_Forum]

I'm not sure, but the choices for this setting are MINIMUM, MAXIMUM, and NORMAL, with NORMAL the default. Usually if a setting is not in the .qsf file, the default is assumed by Quartus II.